83940DY-01LF Ver la hoja de datos (PDF) - Integrated Device Technology
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83940DY-01LF Datasheet PDF : 15 Pages
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83940-01 DATA SHEET
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0° TO 70°
Symbol Parameter
Test Conditions Minimum Typical
VIH
VIL
VPP
VCMR
Input High Voltage
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
PCLK, nPCLK
2
300
VDD - 1.4
IIN
Input Current
VOH
Output High Voltage
IOH = -12mA
1.8
VOL
Output Low Voltage
IOL = 12mA
IDD
Power Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V + 0.3V.
DD
NOTE 2: Common mode voltage is defined as V .
IH
Maximum
VDD
0.8
1000
VDD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f
Output Frequency
MAX
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
1.6
tpLH
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
f 150MHz
1.8
250
MHz
3.0
ns
3.0
ns
PCLK, nPCLK;
NOTE 1, 5
f > 150MHz
1.6
tpLH
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz
1.8
3.3
ns
3.2
ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
85
ps
85
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f 150MHz
f 150MHz
1.4
ns
1.2
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
1.7
ns
1.4
ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
t ,t
Output Rise/Fall Time
RF
20% to 80%
400
odc
Output Duty Cycle
f 150MHz
45
150MHz < f 250MHz
40
850
ps
750
ps
800
ps
55
%
60
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V /2.
DDO
NOTE 2: Measured from V /2 to V /2.
DD
DDO
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V /2.
DDO
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
LOW SKEW, 1-TO-18
4
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
REVISION A 11/4/14
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