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83940DY-01LF

Low Skew, 1-to-18 LVPECL-TO-LVCMOS / LVTTL Fanout Buffer

Integrated Device Technology 

83940-01 DATA SHEET

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF

in the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

OUTPUTS:

CLK INPUT:

For applications not requiring the use of a clock input, it can be

left floating. Though not required, but for additional protection, a

1kΩ resistor can be tied from the CLK input to ground.

LVCMOS OUTPUT:

All unused LVCMOS output can be left floating.We recommend

that there is no trace attached.

PCLK/nPCLK INPUT:

For applications not requiring the use of a differential input,

both the PCLK and nPCLK pins can be left floating. Though not

required, but for additional protection, a 1kΩ resistor can be tied

from PCLK to ground.

LVCMOS CONTROL PINS:

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kΩ resistor can be used.

REVISION A 11/4/14

9

LOW SKEW, 1-TO-18

LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

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