83940DY-01LF Ver la hoja de datos (PDF) - Integrated Device Technology
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83940DY-01LF Datasheet PDF : 15 Pages
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83940-01 DATA SHEET
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
PCLK, nPCLK;
NOTE 1, 5
f 150MHz
1.7
tpLH
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
f 150MHz
1.7
250
MHz
3.2
ns
3.0
ns
PCLK, nPCLK;
NOTE 1, 5
f > 150MHz
1.6
tpLH
Propagation Delay
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz
1.8
3.4
ns
3.3
ns
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
150
ps
150
ps
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f 150MHz
f 150MHz
1.5
ns
1.3
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
1.8
ns
1.5
ns
tsk(pp)
Part-to-Part Skew;
NOTE 4, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @VDDO/2
tR, tF
Output Rise/Fall Time
20% to 80%
400
odc
Output Duty Cycle
f < 134MHz
45
134MHz f < 250MHz
40
850
ps
750
ps
800
ps
55
%
60
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from V /2 to V /2.
DD
DDO
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V /2.
DDO
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V /2.
DDO
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V /2.
DDO
REVISION A 11/4/14
5
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
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