AD8351ARM_04 Ver la hoja de datos (PDF) - Analog Devices

Número de pieza

componentes Descripción

Lista de partido

AD8351ARM_04

Low Distortion Differential RF/IF Amplifier

Analog Devices 

AD8351

It is important to ensure that all I/O, ground, and RG port traces

be kept as short as possible. In addition, it is required that the

ground plane be removed from under the package. Due to the

inverse relationship between the gain of the device and the value

of the RG resistor, any parasitic capacitance on the RG ports can

result in gain-peaking at high frequencies. Following the precau-

tions outlined in Figure 12 will help to reduce parasitic board

capacitance, thus extending the device’s bandwidth and reducing

potential peaking or oscillation.

COPLANAR

WAVEGUIDE

OR ␮STRIP

AGND

RT

RT

1

2

RIP

3

4

RIP

5

10

9

ROP

8

Hi-Z

7

ROP

6

(“de-Q”) the resonant effects of the device bond wires and

surrounding parasitic board capacitance. Typically, 25 Ω series

resistors (size 0402) adequately de-Q the input system without a

significant decrease in ac performance.

Figure 13 illustrates the value of adding input and output series

resistors to help desensitize the resonant effects of board parasitics.

Overshoot and undershoot can be significantly reduced with the

simple addition of RIP and ROP.

1.5

NO RIP OR ROP

1.0

0.5

ROP = 25⍀

0

RIP = ROP = 25⍀

–0.5

RG

AGND

–1.0

Figure 12. General Description of Recommended

Board Layout for High-Z Load Conditions

TRANSMISSION LINE EFFECTS

As noted, stray transmission line capacitance, in combination with

package parasitics, can potentially form a resonant circuit at high

frequencies, resulting in excessive gain peaking. RF transmission

lines connecting the input and output networks should be designed

such that stray capacitance is minimized. The output single-ended

source impedance of the AD8351 is dynamically set to a nominal

value of 75 Ω. Therefore, for a matched load termination, the

characteristic impedance of the output transmission lines should be

designed to be 75 Ω. In many situations, the final load impedance

may be relatively high, greater than 1 kΩ. It is suggested that the

board be designed as shown in Figure 12 for high impedance load

conditions. In most practical board designs, this requires that

the printed-circuit board traces be dimensioned to a small width

(~5 mils) and that the underlying and adjacent ground planes are

far enough away to minimize capacitance.

Typically the driving source impedance into the device will be

low and terminating resistors will be used to prevent input reflec-

tions. The transmission line should be designed to have the

appropriate characteristic impedance in the low-Z region. The

high impedance environment between the terminating resistors

and device input pins should not have ground planes under-

neath or near the signal traces. Small parasitic suppressing

resistors may be necessary at the device input pins to help desensitize

–1.5

0

1

2

3

4

TIME (ns)

Figure 13. Step Response Characteristics with and

without Input and Output Parasitic Suppression Resistors

CHARACTERIZATION SETUP

The test circuit used for 150 Ω and 1 kΩ load testing is provided

in Figure 14. The evaluation board uses balun transformers to

simplify interfacing to single-ended test equipment. Balun effects

need to be removed from the measurements in order to accu-

rately characterize the performance of the device at frequencies

exceeding 1 GHz.

The output L-pad matching networks provide a broadband

impedance match with minimum insertion loss. The input

lines are terminated with 50 Ω resistors for input impedance

matching. The power loss associated with these networks needs

to be accounted for when attempting to measure the gain of the

device. The required resistor values and the appropriate inser-

tion loss and correction factors used to assess the voltage gain

are provided in Table II.

Table II. Load Conditions Specified Differentially

Load

Condition

150 Ω

1 kΩ

R1

43.2 Ω

475 Ω

R2

86.6 Ω

52.3 Ω

Total

Insertion

Loss

5.8 dB

15.9 dB

Conversion

Factor

20 log (S21)

to 20 log (AV)

7.6 dB

25.9 dB

RS

50⍀

BALANCED

SOURCE

RS

50⍀

RT

50⍀

50⍀ CABLE

0.1nF

100nF R1

50⍀ CABLE

RT

50⍀

AD8351

0.1nF DUT

RLOAD

100nF R1

50⍀ CABLE

R2

50⍀ CABLE

R2

50⍀

50⍀ TEST

EQUIPMENT

50⍀

REV. B

Figure 14. Test Circuit

–13–

Share Link: