FM25V01A Ver la hoja de datos (PDF) - Cypress Semiconductor

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FM25V01A

128-Kbit (16K × 8) Serial (SPI) F-RAM

Cypress Semiconductor 

FM25V01A

requires an additional dummy byte. After receiving the opcode,

address, and a dummy byte, the FM25V01A starts driving its SO

line with data bytes, with the MSB first, and continues trans-

mitting as long as the device is selected and the clock is

available. In case of bulk read, the internal address counter is

incremented automatically, and after the last address 3FFFh is

reached, the counter rolls over to 0000h. When the device is

driving data on its SO line, any transition on its SI line is ignored.

The rising edge of CS terminates a fast read operation and

tristates the SO pin. A Fast Read operation is shown in Figure 12.

Figure 10. Memory Write (WREN not shown) Operation

CS

SCK

0 1 2 34 5 670 1 23 4 56 7

12 13 14 15 0 1 2 3 4 5 6 7

Opcode

14-bit Address

Data

SI

0 0 0 0 0 0 1 0 X X A13 A12 A11 A10 A9 A8

A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB MSB

LSB

HI-Z

SO

CS

SCK

SI

SO

Figure 11. Memory Read Operation

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 0 1 2 3 4 5 6 7

Opcode

14-bit Address

0 0 0 0 0 0 1 1 X X A13 A12 A11 A10 A9 A8

A3 A2 A1 A0

MSB

HI-Z

LSB

Data

D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

CS

SCK

SI

SO

Figure 12. Fast Read Operation

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 12 13 14 15 16 17 18 19 20 21 22 23 0 1 2 3 4 5 6 7

Opcode

14-bit Address

Dummy Byte

0 0 0 0 1 0 1 1 X X A13 A12 A11 A10 A9 A8

MSB

HI-Z

A3 A2 A1 A0 X X X X X X X X

LSB

Data

D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

Document Number: 001-90881 Rev. *E

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