ML7012-06 Ver la hoja de datos (PDF) - LAPIS Semiconductor Co., Ltd.
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ML7012-06 Datasheet PDF : 23 Pages
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FEDL7012-06-02
ML7012-06
PIN DESCRIPTIONS
System & Clock
Symbol
OSC0
OSC1
PDN/RST
Type
I
O
I
Description
Pins to connect crystal, resistors and capacitors for the master clock oscillation.
When supplying the master clock from an external source, use OSC0 and leave OSC1 open.
Master clock frequency = 11.0592 MHz. When PDN/RST = “0”, OSC1 outputs “1”.
Refer to the "Connection of Crystal Oscillator" in page 20 for further details.
Power-down and reset control input pin. When PDN/RST = “0”, this device is in the
power-down state and internal circuits are reset.
“0”: Power-down state, “1”: Normal operation
After power-on, set this pin to “0” for 1 µs or more to reset internal circuits.
230 ms (min.) is required to resume normal operation after reset release.
If this pin remains at “0” after power-on, the internal circuits become undefined and the
power-down current may increase. To avoid this, input “1” to this pin and start oscillation or
input the master clock to operate the internal circuits, and then set it to “0”
V.24 Serial Interface
Symbol
STD
Type
I
Transmission data input pin
“0”: Space, “1”: Mark
Description
SRD
RTS
CTS
DCD
DSR
DTR
CI
Receive data output pin
O “0”: Space, “1”: Mark
When PDN/RST = “0”, SRD outputs “1”.
I
RTS (Request to Send) signal input pin
“0”: On, “1”: Off
CTS (Clear to Send) signal output pin
O “0”: On, “1”: Off
When PDN/RST = “0”, CTS outputs “1”.
DCD (Data Carrier Detect) signal output pin
O “0”: On, “1”: Off
When PDN/RST = “0”, DCD outputs “1”.
DSR (Data Set Ready) signal output pin
O “0”: On, “1”: Off
When PDN/RST = “0”, DSR outputs “1”.
I
DTR (Data Terminal Ready) signal input pin
“0”: On, “1”: Off
CI (Calling Indicator) signal output pin (*2)
O “0”: On, “1”: Off
When PDN/RST = “0”, CI outputs “1”.
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