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AN246

STMPE801 - Hardware Interface guide

STMicroelectronics 

Pin description of STMPE801

AN2466

2.5.2

GPIO Level shifting feature

In STMPE801, all GPIO pins are connected to the VIO supply. At reset, all GPIO pins are

LOW and if configured as output, the GPIO pins reach HIGH state only if a '1' is written to

the corresponding bit in the GPSR register. The HIGH state corresponds to the VIO supply

level. This provides a useful level shifting feature without using an explicit level translator

device.

For example, low-voltage processors (Example: 1.8V base-band processors) can directly

control interfacing modules of much higher operating voltages (example 3.6 V drivers)

simply by setting the VIO supply of STMPE801 to the required voltage and setting the GPIO

High/Low by writing into the GPIO registers through the I2C interface.

Figure 8. GPIO Level shifting feature

1.8V

Host

VCC = 1.8V

SCLK

SDATA STMPE801

VIO = 3.6V

GPIO 3.6V

Driver

2.5.3

10/13

GPIO-Hot Key feature

A GPIO is known as 'Hot Key' when it is configured to trigger an interruption to the host

whenever the GPIO input changes state from LOW to HIGH or vice versa. This can also be

used to Wake-up the host processor from Sleep mode.

The GPIO is normally pulled high or pulled low externally with resistors. Any subsequent

change in this logic state triggers an interrupt.

– Programming sequence for Hot Key:

1. The required GPIO pin should be configured as input through the GPDR register.

2. The Global Interrupt (Bit 2) should be enabled by writing '1' and the interrupt polarity

should be set (Bit 0) to active low or active high in the SYSCON register.

3. The ISGPIOR register should be read before enabling the GPIO interrupts in order to

clear any existing interrupt.

4. The individual GPIO interrupts can be enabled by writing '1' into the corresponding bit

in the IEGPIOR register.

5. Now, the port expander is ready to detect the change in logic state on any of the GPIOs

and generate an interrupt to the host processor.

6. Each GPIO state change is reported by the corresponding bit in the ISGPIOR register

and the source of interrupt can be identified by reading the ISGPIOR register. This

permits eight different interrupt sources to be connected to the host through the port

expander. It should be noted that the change of GPIO state is recorded in the ISGPIOR

even if the GPIO interrupt is not enabled in the IEGPIOR.

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