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CY7C1410KV18

36-Mbit QDR® II SRAM 2-Word Burst Architecture

Cypress Semiconductor 

CY7C1410KV18, CY7C1425KV18

CY7C1412KV18, CY7C1414KV18

Contents

Pin Configuration ............................................................. 5

165-ball FBGA (13 × 15 × 1.4 mm) Pinout .................. 5

Pin Definitions .................................................................. 7

Functional Overview ........................................................ 9

Read Operations ......................................................... 9

Write Operations ......................................................... 9

Byte Write Operations ................................................. 9

Single Clock Mode ...................................................... 9

Concurrent Transactions ............................................. 9

Depth Expansion ......................................................... 9

Programmable Impedance .......................................... 9

Echo Clocks .............................................................. 10

PLL ............................................................................ 10

Application Example ...................................................... 10

Truth Table ...................................................................... 11

Write Cycle Descriptions ............................................... 11

Write Cycle Descriptions ............................................... 12

Write Cycle Descriptions ............................................... 12

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13

Disabling the JTAG Feature ...................................... 13

Test Access Port—Test Clock ................................... 13

Test Mode Select (TMS) ........................................... 13

Test Data-In (TDI) ..................................................... 13

Test Data-Out (TDO) ................................................. 13

Performing a TAP Reset ........................................... 13

TAP Registers ........................................................... 13

TAP Instruction Set ................................................... 13

TAP Controller State Diagram ....................................... 15

TAP Controller Block Diagram ...................................... 16

TAP Electrical Characteristics ...................................... 16

TAP AC Switching Characteristics ............................... 17

TAP Timing and Test Conditions .................................. 17

Identification Register Definitions ................................ 18

Scan Register Sizes ....................................................... 18

Instruction Codes ........................................................... 18

Boundary Scan Order .................................................... 19

Power Up Sequence in QDR II SRAM ........................... 20

Power Up Sequence ................................................. 20

PLL Constraints ......................................................... 20

Maximum Ratings ........................................................... 21

Operating Range ............................................................. 21

Neutron Soft Error Immunity ......................................... 21

Electrical Characteristics ............................................... 21

DC Electrical Characteristics ..................................... 21

AC Electrical Characteristics ..................................... 23

Capacitance .................................................................... 24

Thermal Resistance ........................................................ 24

Switching Characteristics .............................................. 25

Switching Waveforms .................................................... 27

Ordering Information ...................................................... 28

Ordering Code Definitions ......................................... 29

Package Diagram ............................................................ 30

Document History Page ................................................. 31

Sales, Solutions, and Legal Information ...................... 31

Worldwide Sales and Design Support ....................... 31

Products .................................................................... 31

PSoC Solutions ......................................................... 31

Document Number: 001-57825 Rev. *C

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