CY7C1410KV18 Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1410KV18 Datasheet PDF : 30 Pages
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CY7C1410KV18, CY7C1425KV18
CY7C1412KV18, CY7C1414KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
CQ
Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the
echo clocks is shown in Switching Characteristics on page 25.
CQ
Echo clock CQ referenced with respect to C. This is a free running clock and is synchronized to the input clock for
output data (C) of the QDR II. In single clock mode, CQ is generated with respect to K. The timing for the
echo clocks is shown in the Switching Characteristics on page 25.
ZQ
Input
Output impedance matching input. This input is used to tune the device outputs to the system data
bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor
connected between ZQ and ground. Alternatively, connect this pin directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL turn off active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the operation with the PLL turned off differs from those listed in this data sheet. For normal operation,
connect this pin to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
TDO
Output TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/72M
Input
Not connected to the die. Can be tied to any voltage level.
NC/144M
Input
Not connected to the die. Can be tied to any voltage level.
NC/288M
Input
Not connected to the die. Can be tied to any voltage level.
VREF
Input- Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
reference measurement points.
VDD
VSS
VDDQ
Power supply Power supply inputs to the core of the device.
Ground Ground for the device.
Power supply Power supply inputs for the outputs of the device.
Document Number: 001-57825 Rev. *C
Page 8 of 30
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