VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Conditions
VG36648041(2)B
-8H
-8L
-10
Unit Notes
Min Max Min Max Min Max
Operating current
ICC1
Burst length = 1
One bank active
CtRKCE ≥ VtRC(MIN.), Io = 0mA
CL = 3
CL = 2
100
100
95
95
90 mA 1
85
Precharge standby
current in power
down mode
ICC 2P
ICC 2PS
CKE ≤ VIH(MAX.) tCK = 15ns
CKE ≤ VIH(MAX.) tCK = ∞
3
3
3 mA
2
2
2
Precharge standby ICC 2N
current in Non - power
down mode
CCKKEE ≥ VIH(MIN.) tCK = 15ns
CCKSE ≥ VIH(MIN.)Input signals are
changed one
time during 2 CLK cycles.
20
20
20 mA
ICC 2NS
CCKKEE ≥VVIH(MIN.), tCK = ∞
CLK ≤VIL(MAX.)
Input signals are stable.
6
6
6
Active standby
current in power
down mode
ICC 3P
ICC 3PS
CKE ≤ VIL(MAX.), tCK = 15ns
CKE ≤ VIL(MAX.), tCK = ∞
5
5
5 mA
4
4
4
Active standby
ICC 3N
current in Nonpower
down mode
CCKKEE ≥ VIH(MIN.), tCK = 15ns
CCKSE ≥ VIH(MIN.)
Input signals are changed
one time during 2CLKs.
25
25
25 mA
ICC 3NS
CCKKEE ≥ VIH(MIN.) tCK = ∞
CLE ≤ VIL(MAX.)
Input signals are stable.
10
10
10
Operating current
ICC4
CtKCKE ≥ VtCK(MIN.)
(Burst mode)
Io = 0mA
All banks Active
CL = 3
CL = 2
160
160
135 mA 2
145
125
105
Refresh current
ICC5
tRC = tRC(MIN.)
CL = 3
CL = 2
130
130
110 mA 3,6
125
125
105
Selfrefresh current ICC6
CKE ≤ 0.2V
2
2
2 mA
lnput Ieakege current ILI
CVKiEn ≥ V0, Vin ≤ VDD + 0.3V
Pins not under test = 0V
- 5 5 - 5 5 - 5 5 uA
Output Ieakege
ILO
CVKouEt ≥ V0, Vout ≤ VDD (MAX)
current
DQ# in H - Z., Dout disabled
- 5 5 - 5 5 - 5 5 uA
Output Low Voltage VOL
lOL = 2mA
0.4
0.4
0.4 V 4
Output High Voltage VOH
lOH = -2mA
2.4
2.4
2.4
V4
Output Low Voltage VOL
lOL = 16mA
VTT
+ 0.8
VTT
+ 0.8
VTT V
5
+ 0.8
Output High Voltage VOH
lOH = -16mA
VTT
+ 0.8
VTT
+ 0.8
VTT
+ 0.8
V5
Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC1 is measured on condition that addresses are changed only one time duringtCK(MIN.).
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK(MIN.).
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
4. For LVTTL compatible, VG3664321(4)1.
5. For SSTL - 3 interface, VG3664321(4)2.
6. Refresh on every 15.6 µ s.
Document : 1G5-0099
Rev.1
Page 6