VG36643241BT-10 Ver la hoja de datos (PDF) - Vanguard International Semiconductor
Número de pieza
componentes Descripción
Lista de partido
VG36643241BT-10 Datasheet PDF : 72 Pages
| |||
VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
A.C Characteristics : (Ta = 0 to 70°C VDD = 3.3V ± 0.3V, VSS = 0V)
Parameter
CLK cycle time (1)
CLK to valid output delay
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
CAS
Latency symbol
3
tck3
2
tck2
3
tAc3
2
tAc2
tCH
tCL
tCKS
tCKH
tAS
tAH
tCMS
tCMH
tDS
VG3664321 (4) 1 (2) B
-8H
-8L
-10
Min Max Min Max Min Max
8
8
10
10
12
15
6
6
6
6
6
6
3
3
3
3
3
3
2
2
3
1
1
1
2
2
3
1
1
1
2
2
3
1
1
1
2
2
3
Data input hold time
tDH
1
1
1
Output data hold time
CLK to output in low - Z
CLK to output in Hi - Z
tOH
3
3
3
tLZ
0
0
0
3
tHZ
6
6
6
2
6
6
6
CLK to output in Hi - Z without load
tOHN
1
1
2
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
tRRD 16
16
20
tRCD 20
20
26
tRP
20
20
26
tRAS 48 120K 48 120K 60 120K
tRC
70
70
90
tBDL
1
1
1
Data - in to ACT(REF) command
Data - in to precharge
Transition time
Mode reg. set cycle
Self refresh exit time
Refresh time
tDAL 1+ tRP
1+ tRP
1+ tRP
tDPL
8
8
10
tT(1)
1
10
1
10
1
10
tT(2) 0.2
5
0.2
5
0.2
5
tRSC
2
2
2
tSRX
1
1
1
tREF
64
64
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
ns
ns
CLK
CLK
ms
Notes : (1) The input clock should be stable and continuous. (jitter ≤ 7% * tCK)
Document : 1G5-0099
Rev.1
Page 8
Share Link: 