PSB4596V3.1 Ver la hoja de datos (PDF) - Siemens AG

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PSB4596V3.1

Analog Line Interface Solution ALIS V3

Siemens AG 

Table 1 PSB 4595 Pin Definitions

Pin No.

Symbol

Function

10

CAP_B22 O

15

CAP_C21 I

14

CAP_C22 I

20

NC

PSB 4595 / PSB 4596

Analog Line Interface Solution

Pin Configuration and Definitions

Descriptions

Must be connected via a capacitor of more

than 5pF to CAP_B12 (PSB 4596)

Must be connected via a capacitor of more

than 5pF to CAP_C11(PSB 4596).

Must be connected via a capacitor of more

than 5pF to CAP_C12 (PSB 4596).

Not Connected.

3.3 Pin Definitions of PSB 4596

Table 2 PSB 4596 Pin Definitions

Pin No.

Symbol

Function

25

VDD

Power

24

GND

Power

21

MCLK1

I

20

MCLK2

O

23

RESET

I

15

FSC

IO

17

DAT_IN

I

Description

+3.3 Volt supply for the digital circuitry.

Ground digital:

all signals are referenced to this pin.

Master Clock1: one pin of a 16.384-MHz-

to-50-MHz crystal is connected. This pin

can also be driven by an external clock.

Master Clock2: other pin of crystal is

connected. When MCLK1 is driven by an

external clock, this pin should be left open.

Reset input: resets the device (low

active).

As input: Frame Synchronization Clock,

identifies the beginning of the frame, FSC

must be synchronous with DAT_CLK.

As output: indicates the beginning of a

new frame.

Serial Data Interface (SDI) : receive data

Parallel Mode:16-bit line data

MUX Mode: 16-bit line data plus 16-bit

control data every FSC.

Semiconductor Group

11

Product Overview 06.98

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