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PSB4596V3.1

Analog Line Interface Solution ALIS V3

Siemens AG 

Table 2 PSB 4596 Pin Definitions

Pin No.

Symbol

Function

16

DAT_OUT O

18

DAT_CLK IO

19

FSC2

O

14

INT

O

7

BM

I

6

SLEEP

O

11

SCI_CLK/ I

MODE

10

SCI_CS/

I

SWAP

12

SCI_IN

I

13

SCI_OUT O

4

ID_Ain

I

5

ID_Bin

I

9

BUZZER O

PSB 4595 / PSB 4596

Analog Line Interface Solution

Pin Configuration and Definitions

Description

Serial Data Interface (SDI) : transmit data,

tristate if not active

Parallel Mode: 16-bit line data

MUX Mode: 16-bit line data plus 16-bit

control data every FSC.

Data clock 256 to 2048 kHz: determines

the rate at which data is transferred to and

from the serial data interface (SDI).

Second FSC to synchronize slave

devices.

Interrupt output pin (open drain, low

active).

Bus Master pin (master or slave mode).

’1’ at the rising edge of RESET activates

Master Mode.

Indicates that PSB 4596 is in the Deep

Sleep Mode.

Serial Control Interface (SCI): clock for

control data.

’1’ at the rising edge of RESET activates

MUX Mode.

Parallel Mode: Serial Control Interface

(SCI): chip select

MUX Mode: to swap 16-bit control data

with 16-bit line data.

Serial Control Interface (SCI): receive

control data from the µC/DSP

(not used in MUX Mode).

Serial Control Interface (SCI): transmit

control data to the µC/DSP

(not used in MUX Mode).

Input for Caller ID comparator A

(connection to TIP).

Input for Caller ID comparator B

(connection to RING).

Output for line monitoring.

Semiconductor Group

12

Product Overview 06.98

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