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FAN5234

Mobile-Friendly PWM/PFM Controller

Fairchild Semiconductor 

PRODUCT SPECIFICATION

FAN5234

Setting the Output Voltage

The internal reference is 0.9V. The output is divided down by

a voltage divider to the VSEN pin (for example, R1 and R2

in Figure 1). The output voltage therefore is:

0----.-9---V--- = V-----O----U----T----–----0---.--9---V---

(9a)

R2

R1

To minimize noise pickup on this node, keep the resistor to

GND (R2) below 2K. We selected R2 at 1.82K. Then choose

R5:

R5 = (---1---.-8---2----K-----)---•----(---1---.-8----V-----–-----0---.-9----) = 1.82K

(9b)

0.9

Output Inductor Selection

The minimum practical output inductor value is the one that

keeps inductor current just on the boundary of continuous

conduction at some minimum load. The industry standard

practice is to choose the ripple current to be somewhere from

15% to 35% of the nominal current. At light load, the ripple

current also determines the point where the converter will

automatically switch to hysteretic mode of operation (IMIN)

to sustain high efficiency. The following equations help to

choose the proper value of the output filter inductor.

∆I

=

2 – IMIN

=

∆-----V----O----U----T-

ESR

(10)

where ∆I is the inductor ripple current, which we will choose

for 20% of the full load current and ∆VOUT is the maximum

output ripple voltage allowed.

L

=

V----F-I--N-S---W-–----V-×----O∆----U-I--T--

×

-V----O----U----T-

VIN

(11)

for this example we'll use:

VIN = 20V, VOUT = 1.8V

∆I = 20% * 3.5A = 0.7A

FSW = 300KHz.

therefore

L ≈ 8µH

Output Capacitor Selection

The output capacitor serves two major functions in a switch-

ing power supply. Along with the inductor it filters the

sequence of pulses produced by the switcher, and it supplies

the load transient currents. The output capacitor require-

ments are usually dictated by ESR, Inductor ripple current

(∆I) and the allowable ripple voltage (∆V).

ESR < ∆--∆---V-I-

(12)

10

For our example,

ESR(MAX)

=

∆--∆---V-I-

=

0----.-1---V---

0.7A

=

142mΩ

In addition, the capacitor's ESR must be low enough to allow

the converter to stay in regulation during a load step. The rip-

ple voltage due to ESR for the converter in Figure 1 is

100mV P-P. Some additional ripple will appear due to the

capacitance value itself:

∆V = -C----O---U----T-----×-∆---8-I----×-----F---S---W---

(13)

which is only about 1.5mV for the converter in Figure 1 and

can be ignored.

The capacitor must also be rated to withstand the RMS cur-

rent which is approximately 0.3 X (∆I), or about 210mA for

our example. High frequency decoupling capacitors should

be placed as close to the loads as physically possible.

Input Capacitor Selection

The input capacitor should be selected by its ripple current

rating. The input RMS current at maximum load current (IL)

is:

IRMS = IL D – D2

(14)

where the converter duty cycle; D = V-----O----U----T- , which for

VIN

the circuit in Figure 1, with VIN=6 calculates to:

IRMS = 1.6A

Power MOSFET Selection

Losses in a MOSFET are the sum of its switching (PSW) and

conduction (PCOND ) losses.

In typical applications, the FAN5234 converter's output volt-

age is low with respect to its input voltage, therefore the

Lower MOSFET (Q2) is conducting the full load current for

most of the cycle. Q2 should be therefore be selected to min-

imize conduction losses, thereby selecting a MOSFET with

low RDS(ON).

In contrast, the high-side MOSFET (Q1) has a much shorter

duty cycle, and it's conduction loss will therefore have less of

an impact. Q1, however, sees most of the switching losses,

so Q1's primary selection criteria should be gate charge.

High-Side Losses:

Figure 8 shows a MOSFET's switching interval, with the

upper graph being the voltage and current on the Drain to

Source and the lower graph detailing VGS vs. time with a

constant current charging the gate. The x-axis therefore is

also representative of gate charge (QG) . CISS = CGD + CGS,

and it controls t1, t2, and t4 timing. CGD receives the current

from the gate driver during t3 (as VDS is falling). The gate

charge (QG) parameters on the lower graph are either speci-

fied or can be derived from MOSFET datasheets.

REV. 1.0.10 5/3/04

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