Introduction
The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device.

FEATUREs
■ Jitter peak-peak (Typical) = 35 ps
■ LVPECL output
■ Default Select option
■ Serially configurable multiply ratios
■ Output edge rate control
■ 16-pin TSSOP
■ High frequency
■ 3.3 V operation

Benefits
■ High accuracy clock generation
■ One pair of differential output drivers
■ Phase-locked loop (PLL) multiplier select
■ 8-bit feedback counter and 6-bit reference counter for high accuracy
■ Minimize electromagnetic interference (EMI)
■ Industry standard, low cost package saves on board space