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LPC61W492 Hoja de datos - SMSC -> Microchip

LPC61W492 image

Número de pieza
LPC61W492

Other PDF
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PDF
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page
160 Pages

File Size
458.7 kB

Fabricante
SMSC
SMSC -> Microchip SMSC

GENERAL DESCRIPTION
The LPC61W492 is an evolving product from SMSCs most popular I/O family. It features a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the next generation Intel chip-set. This interface as its name suggests is to provide an economical implementation of I/Os interface with lower pin count and still maintains equivalent performance as its ISA interface counterpart. Approximately 40 pin counts are saved in LPC I/O comparing to ISA implementation.


FEATURES
▪ 5 Volt Operation
▪ LPC Bus Interface
▪ Supports nLDRQ (LPC DMA), SERIRQ (Serial IRQ)
▪ PC 98/99 and ACPI 1.0 Compliant
▪ Supports DPM (Device Power Management), ACPI
▪ Programmable Configuration Settings
▪ Single 24 or 48 MHz Clock Input
▪ Floppy Disk Controller (FDC)
    - Compatible with IBM PC/AT Disk Drive Systems
    - Variable Write Pre-Compensation with Track Selectable Capability
    - Supports Vertical Recording Format
    - DMA Enable Logic
    - 16-Byte Data FIFOs
    - Supports Floppy Disk Drives and Tape Drives
    - Detects all Overrun and Underrun Conditions
    - Built-in Address Mark Detection Circuit to Simplify the Read Electronics
    - FDD Anti-Virus Functions with Software Write Protect and FDD Write Enable Signal (Write Data Signal was Forced to be Inactive)
    - Supports up to Four 3.5-inch or 5.25- Inch Floppy Disk Drives
    - Completely Compatible with Industry Standard 82077
    - 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2Mbps Data Transfer Rate
    - Supports 3-mode FDD, and its Win95/98 Driver
▪ UART
    - Two High-Speed 16550 Compatible UARTs with 16-byte Send/Receive FIFOs
    - MIDI Compatible
    - Fully Programmable Serial-Interface Characteristics:
    - 5, 6, 7 or 8-bit Characters
    - Even, Odd or No Parity Bit Generation/Detection
    - 1, 1.5 or 2 Stop Bits Generation
    - Internal Diagnostic Capabilities:
    - Loop-back Controls for Communications Link Fault Isolation
    - Break, Parity, Overrun, Framing Error Simulation
    - Programmable Baud Generator Allows Division of 1.8461 MHz and 24 MHz by 1 to (216-1)
    - Maximum Baud Rate up to 921 Kbps for 14.769 MHz and 1.5 Mbps for 24 MHz
(Continue ...)

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