datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga
HOME  >>>  International Cmos Technology  >>> PEEL22LV10AZ PDF

PEEL22LV10AZ Hoja de datos - International Cmos Technology

PEEL22LV10AZ image

Número de pieza
PEEL22LV10AZ

Other PDF
  no available.

PDF
DOWNLOAD     

page
10 Pages

File Size
133 kB

Fabricante
International-Cmos
International Cmos Technology International-Cmos

General Description
The PEEL22LV10AZ is a Programmable Electrically Erasable Logic (PEEL) SPLD (Simple Programmable Logic Device) that operates over the supply voltage range of 2.7V-3.6V and features ultra-low, automatic "zero" power-down operation. The PEEL22LV10AZ is logically and functionally similar to ICTs 5V PEEL22CV10A and PEEL22CV10AZ. The "zero power" (25 µA max. ICC) power-down mode makes the PEEL22LV10AZ ideal for a broad range of batterypowered portable equipment applications, from handheld meters to PCMCIA modems. EEreprogrammability provides both the convenience of product fast reprogramming for product development and quick personalization in manufacturing, including Engineering Change Orders.


FEATUREs
• Low Voltage, Ultra Low Power Operation
    - Vcc = 2.7 to 3.6 V
    - Icc = 5 µA (typical) at standby
    - Icc = 1.5 mA (typical) at 1 MHz
    - Meets JEDEC LV Interface Spec (JESD8-B)
    - 5 Volt tolerant inputs and I/O’s
• CMOS Electrically Erasable Technology
    - Superior factory testing
    - Reprogrammable in plastic package
    - Reduces retrofit and development costs
• Application Versatility
    - Replaces random logic
    - Super set of standard PLDs
    - Pin and JEDEC compatible with 22V10
    - Ideal for battery powered systems
    - Replaces expensive oscillators
• Architectural Flexibility
    - Enhanced architecture fits in more logic
    - 133 product terms x 44 input AND array
    - 12 inputs and 10 I/O pins
    - 12 possible macrocell configurations
    - Asynchronous clear, synchronous preset
    - Independent output enables
    - Programmable clock; pin 1 or p-term
    - Programmable clock polarity
    - 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC
    - Schmitt triggers on clock and data inputs
• Schmitt Trigger Inputs
    - Eliminates external Schmitt trigger devices
    - Ideal for encoder designs

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

Número de pieza
componentes Descripción
PDF
Fabricante
CMOS Programmable Electrically Erasable Logic Device
Ver
International Cmos Technology
CMOS Programmable Electrically Erasable Logic Device
Ver
Anachip Corporation
CMOS Programmable Electrically Erasable Logic Device
Ver
International Cmos Technology
CMOS Programmable Electrically Erasable Logic Device
Ver
Anachip Corporation
CMOS Programmable Electrically Erasable Logic Device
Ver
Anachip Corporation
CMOS Programmable Electrically Erasable Logic Device
Ver
Anachip Corporation
CMOS Programmable Electrically Erasable Logic Device
Ver
Unspecified
CMOS Programmable Electrically Erasable Logic Device
Ver
International Cmos Technology
CMOS Programmable Electrically Erasable Logic Device
Ver
Unspecified
CMOS Programmable Electrically Erasable Logic Device
Ver
International Cmos Technology

Share Link: GO URL

EnglishEnglish Korean한국어 Chinese简体中文 Japanese日本語 Russianрусский

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]