Functional Description
Providing two banks of four outputs, the PI6C2308A is a 3.3V zerodelay buffer designed to distribute clock signals in applications including PC, workstation, datacom, telecom, and high-performance systems. Each bank of four outputs can be controlled by the select inputs as shown in the Select Input Decoding Table.
The PI6C2308A provides 8 copies of a clock signal that has 150ps phase error compared to a reference clock. The skew between the output clock signals for PI6C2308A is less than 200ps. When there are no rising edges on the REF input, the PI6C2308A enters a power down state. In this mode, the PLL is off and all outputs are Hi-Z.This results in less than 12µA of current draw. The Select Input Decoding table shows additional examples when the PLL shuts down. The PI6C2308A configuration table shows all available devices.

Product Features
• 10 MHz to 140 MHz operating range
• Zero input-output propagation delay, adjustable by capacitive load on FBK input
• Multiple configurations, see “Available PI6C2308A Configurations” table
• Input to output delay, less than 150ps
• Multiple low skew outputs
    - Output-output skew less than 200ps
    - Device-device skew less than 500ps
    - Two banks of four outputs, Hi-Z by two select inputs
• Low Jitter, less than 200ps
• 3.3V operation
• Available in industrial &commercial temperatures
• Packages:
    - Space-saving 16-pin, 150-mil SOIC (W)
    - 16-pin TSSOP (L)