Product Description
The PI6C2520 is a low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for Networking Applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing 5 banks of 4 clocks and an extra clock for feedback.

Product Features
• Low-Noise Phase-Locked Loop Clock Distribution.
• Allows Clock Input to have Spread Spectrum modulation for EMI reduction. The clock outputs track the Clock Input modulation.
• Maximum clock frequency of 125 MHz.
• Zero Input-to-Output delay.
• Low jitter: Cycle-to-Cycle jitter –100ps max.
• On-chip series damping resistor at clock output drivers for low noise and EMI reduction.
• Operates at 3.3V VCC.
• Output-to-Output skew less than 200ps.
• Package: Plastic 56-pin TSSOP (A).