Eclipse Family
Combining Performance, Density, and Embedded RAM

Device Highlights
Flexible Programmable Logic
• 0.25 µ, 5 layer metal CMOS process
• 2.5 V Vcc, 2.5/3.3 V dive capable I/O
• Up to 4032 logic cells
• Up to 583,000 max system gates
• Up to 347 I/O

Embedded Dual Port SRAM
• Up to thirty-six 2,304-bit dual port SRAM blocks
• Up to 82,900 RAM bits

Programmable I/O
• High performance: <3.2 ns Tco
• Programmable slew rate control
• Programmable I/O standards:
   LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3
   Eight independent I/O banks
   Three register configurations: input, output and output enable

Advanced Clock Network
• Nine global clock networks 
   One dedicated
   Eight programmable
• Sixteen I/O (high-drive) networks
• Twenty quad-net networks: five per quadrant
• RAM/ROM/FIFO Wizard for automatic configuration
• Configurable and cascadable

APPLICATIONs
• Signal processing operators
• Signal processing functions
• Networking/communications for VoIP
• Speech/voice processing
• Channel coding