datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga
HOME  >>>  QuickLogic Corporation  >>> V363EPC PDF

V363EPC Hoja de datos - QuickLogic Corporation

V363EPC image

Número de pieza
V363EPC

Other PDF
  no available.

PDF
DOWNLOAD     

page
23 Pages

File Size
202.6 kB

Fabricante
QuickLogic
QuickLogic Corporation QuickLogic

The V363EPC offers the highest performance, most flexible, and most economical solution for interfacing either 32-bit or 16-bit local bus applications to the PCI bus. It is also an ideal candidate for a variety of high-performance applications based on Motorola, IBM, DEC, Hitachi, and other popular embedded processors where only a minimal amount of glue logic is needed.
V363EPC is the 3.3 V enhanced version of the V350EPC and V360EPC Rev A1 devices and supports powerful features like Hot Swap and DMA chaining. The PCI bus operates at up to 50 MHz, independent of local bus clock frequency. The overall throughput of the system is dramatically improved by using our unique Dynamic Bandwidth Allocation™ architecture.

About the V363EPC
▼ Direct interface to these processors:
   • AMD® AM29030/40™
   • IBM® PowerPC 401™ Gx
   • Intel® i960® Cx/Hx/Jx/Sx
▼ Fully compliant with PCI Local Bus Specification, Revision 2.1
▼ Configurable for system master, PCI bus master, or PCI target operation
▼ Type 0 and Type 1 PCI configuration cycles
▼ Up to 1 kB burst access on the PCI or the local bus
▼ 640 bytes of programmable FIFO storage with Dynamic Bandwidth Allocation™ architecture
▼ 64-byte read FIFO in each direction
▼ Enhanced support for 8-bit/16-bit local bus devices with programmable region sizes
▼ Dual bi-directional address space remapping
▼ 10-bit bus watch timer
▼ On-the-fly byte order (endian) conversion
▼ I2O-Ready™ ATU and messaging unit, including hardware controlled circular queues
▼ Two-channel DMA, multiprocessor DMA chaining, and demand mode DMA
▼ Hot Swap Capable™ according to the PICMG® Hot Swap Specification, version 2.1
▼ Sixteen 8-bit bi-directional mailbox registers with doorbell interrupts
▼ Support for real-mode MS-DOS® holes
▼ Flexible PCI and local interrupt management
▼ Optional power-on serial EEPROM initialization
▼ Up to 50 MHz on both PCI and local bus clocks
▼ 3.3 V operation; 5 V tolerant input
▼ Industrial temperature range (−40°C to +85°C)
▼ Low-cost 160-pin EIAJ PQFP package (Electronic Industries Association of Japan Plastic Quad Flat Pack)

 

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

Número de pieza
componentes Descripción
PDF
Fabricante
LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS
Ver
QuickLogic Corporation
LOCAL BUS TO PCI BRIDGE FOR MULTIPLEXED A/D PROCESSORS
Ver
QuickLogic Corporation
LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS
Ver
QuickLogic Corporation
LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS
Ver
QuickLogic Corporation
LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS
Ver
QuickLogic Corporation
LOCAL BUS TO PCI BRIDGE FOR DE-MULTIPLEXED A/D PROCESSORS
Ver
Unspecified
PCI Express to Generic Local Bus Bridge
Ver
PLX Technology
PCnet™-PCI Single-Chip Ethernet Controller for PCI Local Bus
Ver
Advanced Micro Devices
PCI Express to PCI Bridge
Ver
Integrated Device Technology
PCI Express to PCI Bridge
Ver
Unspecified

Share Link: GO URL

EnglishEnglish Korean한국어 Chinese简体中文 Japanese日本語 Russianрусский

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]