A8251 Ver la hoja de datos (PDF) - Altera Corporation
Número de pieza
componentes Descripción
Lista de partido
A8251 Datasheet PDF : 21 Pages
| |||
a8251 Programmable Communications Interface Data Sheet
Table 1 describes input and output ports of the a8251.
Table 1. a8251 Ports (Part 1 of 2)
Name
clk
cnd
Type
Input
Input
din[7..0]
extsyncd
Input
Input
ncs
ncts
Input
Input
ndsr
nrd
nrxc
Input
Input
Input
ntxc
nwr
Input
Input
nreset
rxd
dout[7..0]
ndtr
Input
Input
Output
Output
nen
Output
nrts
Output
rxrdy
Output
syn_brk
Output
Polarity
Description
–
–
–
High
Low
Low
Low
Low
Low
Low
Low
Low
–
Low
Low
Low
Low
High
High
Master clock input.
Control/data select. When the cnd signal goes high, the microprocessor
selects status/control data to read/write; otherwise, the microprocessor
selects receiver/transmitter data to read/write.
Parallel data input from the microprocessor or other controlling device.
External sync detect. In synchronous designs, when the extsyncd signal
is asserted, the a8251 begins receiving data on the next rising edge of the
nrxc signal.
Chip select from the microprocessor. When the ncs signal is asserted, all
read or write operations are enabled.
Clear to send, typically a modem signal name. When the ncts signal is
asserted, and if the txen bit of the command instruction register is set, data
transmission is enabled.
Data set ready, typically a modem signal name. The state of this input may
be tested by reading status register bit 7 (dsr).
Read control for the registers. When the nrd and the ncs signals are both
low, the microprocessor reads from the registers.
Receive clock. The receiver control logic samples the nrxd based on the
state of the nrxc signal and the baud rate factor bits in the mode instuction
register.
Transmit clock. Data is asserted to the txd on the falling edge of ntxc.
Write control for the registers. When the nwr and the ncs signals are both
low, the microprocessor writes to the registers.
Asynchronous reset for the registers and control logic.
Receive data. Serial input from the modem or peripheral.
Parallel data output to the microprocessor or other controlling device.
Data terminal ready, typically a modem signal name. Bit 1 of the command
instruction register sets the ndtr signal.
Output enable for the output data bus. When the nen signal is asserted, the
output data is enabled on the dout[7..0] bus line.
Request to send, typically a modem signal name. Bit 5 of the command
instruction register sets the nrts signal.
Receiver ready. A high rxrdy signal indicates that the a8251 has received
a character to be read by the microprocessor.
Sync/break detect. In synchronous operation, when the extsyncd signal
is asserted, the a8251 begins receiving data on the next rising edge of the
nrxc signal. In asynchronous operation, syn_brk indicates a break
condition on rxd.
26
Altera Corporation
Share Link: 