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A8251

Programmable Communications Interface

Altera Corporation 

a8251 Programmable Communications Interface Data Sheet

Baud Rate Factor

Bits 0 and 1 (b1, b2) of the MIR are the baud rate factor bits, which

determine the ratio between the data rate and the clocks. The ratios are

identical when transmitting and receiving. The baud rate factor bits also

provide a means of programming the a8251 for synchronous operation.

Table 3 shows the logic level of the baud rate factor bits and the

corresponding programmed function.

Table 3. Baud Rate Factor Bits

b2

b1

Programmed Function

0

0 Synchronous operation.

0

1 Divide-by-1 mode. Clock and data rates are identical. External

logic is responsible for synchronizing the rxd signal to the

nrxc signal. The rxd signal is sampled on the rising edge of

the nrxc signal, and the txd signal is asserted on the falling

edge of the ntxc signal.

1

0 Divide-by-16 mode. The clock rate is 16 times the data rate.

After start bit detection (rxd low), the rxd signal is sampled on

the ninth rising edge of nrxc. After writing to the transmitter

register, the txd signal is asserted on the first falling edge of

the ntxc signal and every 16 clocks thereafter.

1

1 Divide-by-64 mode. The clock rate is 64 times the data rate.

After start bit detection (rxd low), the rxd signal is sampled on

the 33rd rising edge of the nrxc. After writing to the transmitter

register (assuming the transmission is enabled), txd is

asserted on the first falling edge of the ntxc signal and every

64 clocks thereafter.

Word Length Select

Bits 2 and 3 (l1, l2) of the MIR are the word length select bits, which are

used to select the character length of the data byte. Table 4 shows the logic

level of the word length select bits and the corresponding word length.

Altera Corporation

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