HS-80C86RH(1995) Ver la hoja de datos (PDF) - Intersil

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HS-80C86RH
(Rev.:1995)

Radiation Hardened 16-Bit CMOS Microprocessor

Intersil 

Waveforms (Continued)

HS-80C86RH

CLK

TINVCH (SEE NOTE)

NMI

INTR SIGNAL

TEST

FIGURE 11. ASYNCHRONOUS SIGNAL RECOGNITION

NOTE: Setup Requirements for

asynchronous signals only to

guarantee recognition at next CLK.

CLK

TCLAV

ANY CLK CYCLE

TCLAV

ANY CLK CYCLE

LOCK

FIGURE 12. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

VCC

≥ 50µs

CLK

TCLDX

TDVCL

RESET

≥ 4 CLK CYCLES

FIGURE 13. RESET TIMING

CLK

TCLGH

RQ/GT

TCLCL

PREVIOUS GRANT

AD15-AD0

ANY

CLK

CYCLE

≥ 0-CLK

CYCLES

TCLGL

TCLGH

TGVCH

TCHGX

PULSE 1

COPROCESSOR

RQ

HS-80C86RH

PULSE 2

HS-80C86RH

GT

TCLAZ

PULSE 3

COPROCESSOR

RELEASE

RD, LOCK

BHE/S7, A19/S6-A16/S3

S2, S1, S0

TCHSZ

(SEE NOTE) TCHSV

NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.

FIGURE 14. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

CLK

HOLD

HLDA

AD15-AD0

≥ 1CLK

CYCLE

THVCH

80C86

1 OR 2

CYCLES

THVCH

TCLHAV

TCLAZ

COPROCESSOR

TCLHAV

80C86

BHE/S7, A19/S6-A16/S3

RD, WR, M/IO, DT/R, DEN

TCHSZ

FIGURE 15. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

Spec Number 518055

879

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