HS-80C86RH(1995) Ver la hoja de datos (PDF) - Intersil
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HS-80C86RH Datasheet PDF : 37 Pages
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HS-80C86RH
AC Test Circuit
OUTPUT FROM
DEVICE UNDER TEST
CL (Note)
NOTE: Includes stray and jig capacitance.
AC Testing Input, Output Waveform
TEST POINT
INPUT
VIH
VIL - 0.4V
1.5V
1.5V
OUTPUT
VOH
VOH
NOTE: All inputs signals (other than CLK) must switch between VIL
Max -0.4V and VIH Min +0.4. CLK must switch between 0.4V
and VDD -0.4V. TR and TF must be less than or equal to
15ns. CLK TR and TF must be less than or equal to 10ns.
Burn-In Circuits
HS-80C86RH 40 PIN DIP
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
19
20
40
F15
39
F14
38
F13
37
F12
36
F11
35
F10
34
F9
33
F8
32
F7
31
F6
30
F5
29
F4
28
F3
27
F2
26
F1
25
NMI
24
23
F0
22
21
T
T ≥ 5.0µs
HS-80C86RH 40 PIN DIP
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
VDD
2.7KΩ
LOAD
2.7KΩ
VDD
F16
LOAD
LOAD
LOAD
LOAD
LOAD
MN/MX
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
LOAD
READY
RESET
STATIC
VDD = +6.5V ±10%
TA = +125oC Minimum
Part is Static Sensitive
Voltages Must Be Ramped
Package: 40 Lead DIP
Resistors:
10kΩ ±10%
(Pins 17, 18, 21-23, 31, 33)
2.7kΩ ±5% (Pins 2-16, 39)
1.0kΩ ±5% 1/10W Min (Pin 19)
Minimum of 5 CLK Pulses
After Initial Pulses, CLK is Left High
Pulses are 50% Duty Cycle Square
Wave
DYNAMIC
VDD = 6.5V ±5% (Burn-In)
VDD = 6.0V ±5% (Life Test)
TA = +125oC
Package: 40 Lead DIP
Part is Static Sensitive
Voltage Must Be Ramped
Resistors:
10kΩ (Pins 17, 18, 21, 22, 23, 33)
3.3kΩ (Pins 2-16, 19, 30, 31, 39)
2.7kΩ Loads As Indicated
All Resistors Are At Least 1/8W,
±10%
F0 = 100kHz, F1 = F0/2, F2 = F1/2 . . .
RESET, NMI low after initialization.
READY pulsed low every 320ms
MN/MX changes state every 5.24s
Spec Number 518055
880
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