GLT6400M16(2001) Ver la hoja de datos (PDF) - G-Link Technology

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GLT6400M16
(Rev.:2001)

Ultra Low Power 256k x 16 CMOS SRAM

G-Link Technology  

G-LINK

GLT6400M16

Ultra Low Power 256k x 16 CMOS SRAM

May 2001(Rev. 1.1)

Notes :

1. L-version includes this feature.

2. This Parameter is samples and not 100% tested.

3. For test conditions, see AC Test Condition.

4. This parameter is tested with CL = 5pF. Transition is measured ± 500mV from steady – state voltage.

5. This parameter is guaranteed, but is not tested.

6. WE is HIGH for read cycle.

7. CE1 and OE are LOW and CE2 is HIGH for read cycle.

8. Address valid prior to or coincident with CE1 transition LOW or CE2 transition HIGH.

9. All read cycle timings are referenced from the last valid address to the first transition address.

10. CE1 or WE must be HIGH or CE2 must be LOW during address transition.

11. All write cycle timings are referenced from the last valid address to the first transition address.

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