GLT6400M16(2001) Ver la hoja de datos (PDF) - G-Link Technology
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GLT6400M16 Datasheet PDF : 13 Pages
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G-LINK
GLT6400M16
Ultra Low Power 256k x 16 CMOS SRAM
May 2001(Rev. 1.1)
Features :
Description :
∗ Low-power consumption.
The GLT6400M16 is a low power CMOS Static
-Active: 30mA Icc at 120ns.
RAM organized as 262,144 words by 16 bits. Easy
-Stand by :
memory expansion is provided by an active LOW
20 µA (CMOS input / output , LL)
CE1 and OE pin and active HIGH CE2.
5 µA (CMOS input / output, SL)
∗ Single +2.3V to 2.7V Power Supply.
∗ Equal access and cycle time.
∗ 120 ns access time.
∗ Tri-state output.
This device has an automatic power – down
mode feature when deselected. Separate Byte
Enable controls ( BLE and BHE ) allow individual
bytes to be accessed. BLE controls the lower bits
∗ Automatic power-down when
I/O0 – I/O7. BHE controls the upper bits I/O8 –
deselected.
I/O15.
∗ Multiple center power and ground pins
Writing to these devices is performed by taking
for improved noise immunity.
∗ Individual byte controls for both Read
and Write cycles.
Chip Enable CE1 with Write Enable WE and byte
Enable ( BLE / BHE ) Low while CE2 remains
∗ Industrial grade (-40°C ~ 85°C)
available.
HIGH.
Reading from the device is performed by taking
∗ Available in 48-fpBGA/44L TSOPII.
Chip Enable CE1 with Output enable OE and byte
∗ CE2 pin available for fpBGA only.
Enable ( BLE / BHE ) Low while Write Enable WE
and CE2 are held HIGH.
Function Block Diagram :
Pre-Charge Circuit
Vcc
Vss
Memory Array
2048 x 2048
I/O0 - I/O7
I/O8 - I/O15
Data
Circuit
Data
Circuit
I/O Circuit
Column Select
Column Address
WE
OE
BHE
BLE
CE1
CE2
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
Control
Logic
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G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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