datasheetbank_Logo
búsqueda de Hoja de datos y gratuito Fichas de descarga

DM9101E Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.

Número de pieza
componentes Descripción
Lista de partido
DM9101E Datasheet PDF : 43 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Pin Description (continued)
DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Pin No.
Pin Name
I/O
Description
LQFP QFP
PHY Address Interface:
PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a
PHY isolation condition. See the isolate bit description in the BMCR, address 00.
81
83
PHYAD0
I PHY Address 0:
PHY address bit 0 for multiple PHY address applications. The
status of this pin is latched into Register 17, bit 8 during power
up/reset.
82
84
PHYAD1
I PHY Address 1:
PHY address bit 1 for multiple PHY address applications. The
status of this pin is latched into Register 17, bit 7 during power
up/reset.
83
85
PHYAD2
I PHY Address 2:
PHY address bit 2 for multiple PHY address applications. The
status of this pin is latched into Register 17, bit 6 during power
up/reset.
86
88
PHYAD3
I PHY Address 3:
PHY address bit 3 for multiple PHY address applications. The
status of this pin is latched into Register 17, bit 5 during power
up/reset.
87
89
PHYAD4
I PHY Address 4:
PHY address bit 4 for multiple PHY address applications. The
status of this pin is latched into Register 17, bit 4 during power
up/reset.
Miscellaneous
1-3,
2 - 5,
NC
17, 18, 19, 20,
44,
46
100
No Connect:
Leave these pins unconnected (floating).
33
35
BGREF
I Bandgap Voltage Reference:
Connect a 6.01K, 1% resistor between this pin and the BGRET
pin to provide an accurate current reference for the DM9101.
34
36
BGRET
I Bandgap Voltage Reference Return:
Return pin for 6.01Kresistor connection.
39
41
TRIDRV
I Tri-state Digital Output Pins:
When set high, all digital output pins are set to a high impedance
state, and I/O pins, go to input mode.
79
81
RESET#
I Reset: Active Low input that initializes the DM9101. It should
remain low for 30ms after VCC has stabilized at 5Vdc (normal)
before it transitions high.
80
82 TESTMODE I Test Mode Control Pin:
TESTMODE=0: Normal operating mode.
TESTMODE=1: Enable test mode.
10
Final
Version: DM9101-DS-F03
July 22, 1999

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]