DM9101E Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9101E Datasheet PDF : 43 Pages
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Pin Description (continued)
DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Pin No.
Pin Name
I/O
Description
LQFP QFP
Device Configuration/Control/Status Interface (continued)
88-91
90 - 93
OPMODE0
OPMODE1
OPMODE2
OPMODE3
I OPMODE0 - OPMODE3:
These pins are used to control the forced or advertised operating
mode of the DM9101 (see table below). The value is latched into
the DM9101 registers at power-up/reset.
OPMODE3
0
0
0
0
0
0
0
0
1
1
OPMODE2
0
0
0
0
1
1
1
1
0
0
OPMODE1
0
0
1
1
0
0
1
1
0
0
OPMODE0
0
1
0
1
0
1
0
1
0
1
Function
Auto-neg enable
with all
capabilities with
Flow Control
Auto-neg enable
without all
capabilities
without Flow
Control
Auto-neg 100TX
FDX with Flow
Control only
Auto-neg 100TX
FDX/HDX
without Flow
Control
Auto-neg 10TP
FDX with Flow
Control only
Auto-neg 10TX
FDX/HDX
without Flow
Control
Manual select
100TX FDX
Manual select
100TX HDX
Manual select
10TX FDX
Manual select
10TX HDX
92
94 RTPR/NOD
I Repeater/Node Mode:
E#
When set high, this bit selects REPEATER mode; when set low, it
selects NODE. In REPEATER mode or NODE mode with Full
Duplex configured, the Carrier Sense (CRS) output from the
DM9101 will be asserted only during receive activity. In NODE
mode or a mode not configured for Full Duplex operation, CRS will
be asserted during receive or transmit activity. At power-up/reset,
the value on this pin is latched into Register 16, bit 11.
93
95
BPALIGN
I Bypass Alignment:
Allows 100Mbps transmit and receive data streams to bypass all
of the transmit and receive operations when set high.
At power-up/reset, the value on this pin is latched into bit Register
16 ,bit 13.
8
Final
Version: DM9101-DS-F03
July 22, 1999
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