DM9101E Ver la hoja de datos (PDF) - Davicom Semiconductor, Inc.
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DM9101E Datasheet PDF : 43 Pages
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DM9101
10/100Mbps Ethernet Physical Layer Single Chip Transceiver
Features
• 10/100Base-TX physical-layer, single-chip transceiver
• Compliant with IEEE 802.3u 100Base-TX standard
• Compliant with ANSI X3T12 TP-PMD 1995 standard
• Compliant with IEEE 802.3u Auto-negotiation protocol
for automatic link type selection
• Supports the MII with serial management interface
• Supports Full Duplex operation for 10 and 100Mbps
• High performance 100Mbps clock generator and data
recovery circuitry
• Adaptive equalization circuitry for 100Mbps receiver
• Controlled output edge rates in 100Mbps
• Supports a 10Base-T interface without the need for
an external filter
• Provides Loop-back mode for system diagnostics
• Includes Flexible LED configuration capability
• Digital clock recovery circuit using advanced digital
algorithm to reduce jitter
• Low-power, high-performance CMOS process
• Available in both a 100 pin LQFP and a 100 QFP
package
Pin Configuration: DM9101E LQFP
NC
1
NC
2
NC
3
AGND
4
AVCC
5
AVCC
6
RXI-
7
RXI+
8
AGND
9
AGND
10
10TXO-
11
10TXO+
12
AVCC
13
AVCC
14
AGND
15
AGND
16
NC
17
NC
18
AVCC
19
AVCC
20
AGND
21
AGND
22
100TXO-
23
100TXO+
24
AVCC
25
DM9101E
75
COL
74
CRS
73
RX_CLK
72
DVCC
71
DGND
70
RXD0
69
RXD1
68
RXD2
67
RXD3
66
DVCC
65
DGND
64
MDIO
63
MDC
62
TX_CLK
6
1
TX_EN
60
DVCC
59
DGND
58
TXD0
57
TXD1
56
TXD2
55
TXD3
54
TX_ER/TXD4
53
TXLED#
52
RXLED#
5
1
LINKLED#
Final
3
Version: DM9101-DS-F03
July 22, 1999
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