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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

The copy may begin before the entire frame has

been received if early receive is enabled. When

the header copy is complete, the receive DMA

status will then be posted to the descriptor for

the header buffer, and the header copy complete

interrupt will be set. If reception from the

network has completed, the network portion of

the posted status will be valid --and the RSV bit

will be set to 1. In early receive mode, the

receive DMA status may be posted before the

network status for the frame is available, in

which case the RSV bit in the descriptor will be

set to 0. If the entire frame fits into the header

buffer, the network receive status will always be

posted with the frame. After a header copy, the

receive DMA always clears the RXQUEUED bit

(also setting the receive queue empty interrupt,

which may be masked) and waits in the idle

state for the software driver to queue a

fragment list for the rest of the frame.

After examining the header data, the software

driver may discard the frame or have it copied

into host memory as many times as it would

like. The software requests copies of the frame

by programming descriptors (and fragments

lists) and setting RXQUEUED without setting

NEXTFRAME. The frame is copied exactly as it

would be in the free buffer pool mode, with the

exception that the offset field is used with

fragment list copies. The software may not

need all of the bytes at the beginning of the

frame to be copied, so it may specify an offset

into the frame where the copy should begin. The

offset field shares a location in the descriptor

with the buffer length field because the buffer

length is not specified in a descriptor for a

fragment list. The receive DMA copies the frame

into host memory beginning from the byte

number specified in the offset. If the offset field

is not zero, the copy will not begin until the

entire frame has been received from the

network, even if early receive is enabled. This is

so that the receive DMA does not copy invalid

data if the offset is greater than the number of

bytes that have been received so far. Usually,

the entire frame will have been received before

the fragment list is available.

When the copy is finished, the receive status is

posted and the receive copy complete interrupt

is set. The receive DMA will then read the next

descriptor, and if the ownership bit is set it will

immediately begin to copy the same frame into

host memory again. If the descriptor is owned

by the host, RXQUEUED will be cleared (and

receive queue empty interrupt set) and the

receive DMA will wait in the idle state for

another command. If the software driver wants

another copy of the frame, it may queue another

descriptor and set RXQUEUED without setting

NEXTFRAME. This procedure will be repeated

until the software chooses to go on to the next

frame.

The software driver discards a frame by setting

NEXTFRAME before or simultaneous to setting

RXQUEUED. If RXQUEUED is set after or

along with NEXTFRAME, the receive DMA will

begin to copy the next frame (if any) in the

receive buffer. The next descriptor queued

should contain a header buffer for the next

frame.

Occasionally, the software driver may want to

discard a frame immediately after reading its

header, but still read the receive status for that

frame. If the valid network status is not posted

in the descriptor, the software driver may read it

from the PRSTAT register. The driver must set

NEXTFRAME and RXQUEUED to discard the

frame first, as described above. However, the

next descriptor in the receive descriptor list must

have the ownership bit cleared (host still owns

descriptor). This allows the LAN83C171 to

update the PRSTAT register without starting to

copy the following frame. The software driver

must poll the RQE (receive queue empty)

interrupt to determine when the status is

available. When the RQE interrupt is set, the

driver may read the receive status from the

PRSTAT register. The receive status valid bit in

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