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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

Interframe Gap and Deference

Deference is initiated when both CRS and COL

have terminated at the end of a packet. The

transmitter deference logic initiates a 2-part

timer at the end of network activity. While this

timer is running, no frame transmission will be

initiated. The first part of the timer (interFrame

SpacingPart1) is used to observe the network

for transmission activity by other stations. If this

station is transmitting, carrier is sensed, or

collision is detected during this part of the timer,

the timer will be reset to zero and held there

until the termination of line activity. When the

first part of the timer elapses, line activity is no

longer observed and the timer runs to

completion.

If any frame is queued up for transmission at

the moment of timer expiration, transmission

will be initiated regardless of line activity.

The combination of interFrame SpacingPart1

and interFrame SpacingPart2 makes up the

Inter-Frame Gap (IFG) as defined by the 802.3

specification.

Collision Handling Logic

When collision is detected by the transmitter

section during the first slot timer of an active

transmission, the transmission terminates after

completion of the preamble and the jam

sequence. The jam sequence is 32 bits of logic

'1's. If collision is detected after the slot time is

passed, the transmission will be aborted after

the jam sequence. An out of window collision

interrupt will be generated and the collision

count status will be retained in the transmit

status register for software collection. After the

software has responded to the interrupt and re-

enabled transmissions, the transmit status will

be cleared and the packet will be automatically

retransmitted.

Timers and Counters/Slot Timer

During transmit, the slot timer starts counting

once the receiver recognizes that a carrier is

present at the start of a returning preamble.

When backing off, the slot timer starts with the

end of transmit enable (TX_EN) for the collided

frame and is not reset by any other incoming

frames. The slot timer is programmable by the

transmit control register. The default slot time is

512 bit times.

Backoff Timer

After a transmission is terminated because of a

collision, a retransmission is attempted. The

backoff time is determined by the truncated

binary exponential backoff algorithm. This

algorithm is:

Draw a random integer r such that r 0<=r<2**k

k is the number of retries already on this

transmission. The value k is initialized to 0.

The required backoff time is 'r' number of slot

times. After the backoff time has been

completed, normal transmission deferral begins.

The backoff timer is a 12 bit counter that is

initialized to a random number when an

attempted transmission results in a collision.

The counter decrements once per slot time until

it reaches zero. The transmit protocol FSM

utilizes this timer to insert a variable amount of

delay ahead of its attempt to retransmit the

frame.

Collision Counter

Prior to the first attempt at each frame

transmission, the collision counter is initialized

to 0. Each attempted transmission of the frame

resulting in a collision causes the collision

counter to increment. If the maximum number

of collisions (16) is reached before a successful

attempt to transmit the frame, the frame

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