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LAN83C171

EPIC/XF ACPI/PC 97 Compliant Integrated PCI 10/100 Mbps Fast Ethernet Controller

SMSC -> Microchip 

transmission is aborted. An interrupt is

generated for an aborted frame indicating

transmission complete, and the collision count

value in the transmit status register is 16.

Heartbeat Detection

When the transmitter is configured in serial

mode, after each transmission, the transmit

logic opens a window 3.6µsec long during which

it looks for a pulse on the COL pin. This pulse

is normally generated by the MAU and is

received through the MII interface. If the pulse

is received, the CDH status bit of the transmit

status register is cleared. If no pulse is received,

the CDH bit is set.

MAC RECEIVER

The LAN83C171 CSMA/CD receiver is capable

of operating with network data rates of 10 and

100Mb/s. It supports current implementations

of 10Mb/s physical layer devices, and the

802.3u Media Independent Interface for 10 and

100Mb/s.

Basic Function

The receiver processes serial or nibble wide

data streams at data rates of 10Mb/s or

100Mb/s. The receiver detects start of frame,

provides destination address recognition and

filtering, transfers recognized frames to

memory, and provides error detection and

reporting.

Interface to Physical Layers

The receiver interfaces to the physical layer in

serial or parallel mode. When in the serial

mode, data is transferred serially on the RXD[0]

pin synchronous to the falling edge of the

receive data clock (RX_CLK). RX_CLK is a

10MHz clock signal recovered by the physical

layer device from the data stream. The CRS

and COL signals provide carrier sense and

collision detect respectively.

In parallel mode, the physical layer device

transfers data to the LAN83C171 four bits at a

time on the RXD[3-0] data bus. The data is

transferred synchronously to the falling edge of

RXC. The signal Receive Data Valid (RX_DV)

informs the MAC of the RXD bus status. The

physical layer can also notify the LAN83C171 of

invalid data on the medium with the Receive

Error signal (RX_ER). Selecting the receiver

interface mode is performed by programming

the MII Configuration register.

Packet Reception/Serial Mode

After detection of carrier, serial bits received on

RXD[0] are synchronized to the rising edge of

RX_CLK. Each bit is shifted through an 8 bit

shift register scanning for a Start of Frame

Delimiter (SFD) pattern of '10101011' received

from left to right. Following detection of SFD, all

bits are byte aligned in the serial to parallel shift

register. Bits are received from least significant

bit to most significant bit within the byte. Data

from the shift register is transferred to the

receive FIFO where it waits for the receive DMA

to transfer it into local memory. The receive

process continues while CRS or COL are

active.

Parallel Mode

Packet reception begins with the first nibble after

detecting RX_DV active. Nibbles transferred on

RXD[3-0] are synchronized to the rising edge of

RX_CLK and shifted into a 2-nibble shift

register. RXD[0] is the least significant bit

(LSB). SFD is detected when the shift register

contains the value '10101011' from LSB to

MSB. The preamble and SFD pattern received

from the PHY device is required to be nibble

aligned. Bytes are aligned in the 2-nibble shift

register after detection of SFD. Each byte is

transferred to the receive FIFO. Packet

reception continues while RXDV is active and

ends with the nibble preceding the falling edge

of RX_DV. While RX_DV is de-asserted, the

value of RXD[3-0] has no effect on the MAC.

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