LAN83C171 Ver la hoja de datos (PDF) - SMSC -> Microchip
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LAN83C171
SMSC -> Microchip
LAN83C171 Datasheet PDF : 90 Pages
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request to the local receive memory is made.
The return of acknowledge is guaranteed to
prevent the receive FIFO from overflowing. The
data path to the receive local memory is 32 bits.
If the receive local memory becomes full during
reception of a frame, the frame is aborted. The
host is notified of the condition with an overflow
interrupt. Additionally, the missed packet
counter is incremented for each frame which
could not be received due to the overflow
condition.
Monitor Mode
The data transfer process can be inhibited by
operating in monitor mode. This mode checks
validity of incoming frames and maintains error
statistics, but does not store the frame in
memory. Frames, which would otherwise have
been accepted, cause the Missed Packet
counter (MPCNT) to increment upon completion
of the frame.
MPCNT register records the number of overflow
packets when the EPIC is operating in normal
mode. It's function changes when in monitor
mode and counts the number of packets that
were meant for this node but not saved.
Error Checking
Received frames are checked for CRC and
alignment errors. If the CRC of a received
frame is incorrect, a CRC error is indicated in
the status register and the CRC error counter is
incremented. Reception of the frame is aborted
unless the receiver has been programmed to
receive errored packets. If the frame does not
terminate on a byte boundary and the CRC is
incorrect, then an alignment error is also
indicated in the status register. When this
occurs, the alignment error counter will be
incremented. A receive error interrupt is
generated when a CRC error is detected and
monitor mode is not set.
The receive control register can be programmed
to enable long frame checking (frames longer
than 1518 bytes). When a long frame is
detected the CRC and alignment counters are
not incremented.
Status
A status register is updated at the completion of
each frame whether it completed normally or
aborted in error. The status register holds
important information about the frame until it is
transferred with the packet data to the receive
local memory. If the frame data is not being
saved due to an error or monitor mode, then the
contents of the status register will be lost after
the completion of the following packet. A
description of the status register contents is
located in the register definition section of this
data sheet.
Event Counters
Three event counters record CRC errors,
alignment errors, and missed packets. The
counters are all 8 bits wide and count from zero
to 255. At 255 the counters stop until they have
been read by the host. The counters are self
clearing after the read. The counters generate a
shared interrupt when any one of them reaches
a count of 192.
The counter is also incremented for receive local
memory full errors. The missed packet counter
is 8 bits wide and generates an interrupt when
it reaches a count of 192.
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