DM9102A Ver la hoja de datos (PDF) - Unspecified

Número de pieza

componentes Descripción

Lista de partido

DM9102A

Single Chip Fast Ethernet NIC controller

Unspecified 

7

0

6

0

5

0

4

0

3

0

2

1

1

1

0

1

DM9102A

Single Chip Fast Ethernet NIC controller

and bit 6 are set.

RO

Address/Data Stepping (0 For No Stepping)

RW

Parity Error Response Enable/Disable

Setting this bit will enable the DM9102A to assert PERR# on the detection

of a data parity error and to assert SERR# for reporting address parity

error.

RO

VGA Palette Snooping (0 For Not Support)

RO

Memory Write and Invalid (0 For Not Implementation)

The DM9102A only generates Memory write cycle.

RO

Special Cycles (0 For Not Implementation)

RW

Master Device Capability Enable/Disable

When this bit is set, DM9102A has the ability of master mode operation.

RW

Memory Space Access Enable/Disable

This bit controls the ability of memory space access. The memory access

includes memory mapped I/O access and Boot ROM access. As the

system boots up, this bit will be enabled by BIOS for Boot ROM memory

access. While in normal operation using memory mapped I/O access, this

bit should be set by driver before memory access cycles.

RW

I/O Space Access Enable/Disable

This bit controls the ability of I/O space access. It will be set by BIOS after

power on.

Revision ID (xxxxxx08 - PCIRV)

31

Class Code

Revision Major Number

Revision Minor Number

Class Code

87

43

0

Revision ID

Bit

Default

31:8 020000h

7:4

0011

3:0

0001

Type

RO

RO

RO

Description

Class Code (020000h)

This is the standard code for Ethernet LAN controller.

Revision Major Number

This is the silicon-major revision number that will increase for the subsequent

versions of the DM9102.A.

Revision Minor Number

This is the silicon-minor revision number that will increase for the subsequent

versions of the DM9102A.

Final

17

Version: DM9102A-DS-F03

August 28, 2000

Share Link: