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DM9102A

Single Chip Fast Ethernet NIC controller

Unspecified 

Miscellaneous Function (xxxxxx0c - PCILT)

DM9102A

Single Chip Fast Ethernet NIC controller

31

BIST

24 23

16 15

87

0

Header Type

Latency Timer

Cache Line Size

Built-In Self Test

Header Type

Latency Timer For The Bus Master

Cache Line Size For Memory Read

Bit

31:24

23:16

15:8

Default

00h

00h

00h

7:0

00h

Type

RO

RO

RW

RO

Description

Built In Self Test ( 00h Means Not Implementation)

Header Type ( 00h Means single function with Predefined Header Type )

Latency Timer For The Bus Master.

The latency timer is guaranteed by the system and measured by clock cycles.

When the FRAME# asserted at the beginning of a master period by the DM9102A,

the value will be copied into a counter and start counting down. If the FRAME# is

de-asserted prior to count expiration, this value is meaningless. When the count

expires before GNT# is de-asserted, the master transaction will be terminated as

soon as the GNT# is removed.

While GNT# signal is removed and the counter is non-zero, the DM9102A will

continue with its data transfers until the count expires. The system host will read

MIN_GNT and MAX_LAT registers to determine the latency requirement for the

device and then initialize the latency timer with an appropriate value.

The reset value of Latency Timer is determined by BIOS.

Cache line Size For Memory Read Mode Selection ( 00h Means Not

Implementation For Use)

I/O Base Address (xxxxxx10 - PCIIO)

31

I/O Base Address

I/O Base Address

PCI I/O Range

I/O or Memory Space Indicator

87

10

0000000

1

18

Final

Version: DM9102A-DS-F03

August 28, 2000

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