MX98725 Ver la hoja de datos (PDF) - Macronix International

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MX98725

SINGLE CHIP FAST ETHERNET NIC CONTROLLER

Macronix International 

MX98725

4. PIN DESCRIPTION ( 160 PIN PQFP )

( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain )

Pin Name

AD[31:0]

Type

T/S

CBEB[3:0] T/S

FRAMEB S/T/S

TRDYB

S/T/S

IRDYB

S/T/S

DEVSELB S/T/S

IDSEL

PCICLK

RSTB

INTAB

SERRB

PERRB

I

I

I

O/D

O/D

S/T/S

Pin No.

20,21,23,24,

27,32,33,36,

41,37,38,42,

44,45,48,49,

51,52,66,69,

70,73,74,75,

78,79,82,83,

86,87,90,91,

93,94

37,53

65,80

54

58

57

59

38

17

16

15

63

62

160 Pin Function and Driver

PCI address/data bus: shared PCI address/data bus lines. Little or

big endian byte ordering are supported.

PCI command and byte enable bus: shared PCI bus command and

byte enable bus, during the address phase of the transaction, these

four bits provide the bus command. During the data phase, these four

bits provide the byte enable.

PCI FRAMEB signal: shared PCI cycle start signal, asserted to

indicate the beginning of a bus transaction. As long as FRAMEB is

asserted, data transfers continue.

PCI Target ready: issued by the target agent, a data phase is

completed on the rising edge of PCICLK when both IRDYB and

TRDYB are asserted.

PCI Master ready: indicates the bus master's ability to complete

the current data phase of the transaction. A data phase is completed on

any rising edge of PCICLK when both IRDYB and TRDYB are asserted.

PCI slave device select: asserted by the target of the current bus

access. When MX98725 is the initiator of current bus access, the target

must assert DEVSELB within 5 bus cycles, otherwise cycle is aborted.

PCI initialization device select: target specific device select signal for

configuration cycles issued by host.

PCI bus clock input: PCI bus clock range from 16MHz to 33MHz.

PCI bus reset: host system hardware reset.

PCI bus interrupt request signal: wired to INTAB line.

PCI bus system error signal: If an address parity error is detected and

CFCS bit 8 is enabled, SERRB and CFCS’s bit 30 will be asserted.

PCI bus data error signal: As a bus master, when a data parity error is

detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will

be asserted. As a bus target, a data parity error will cause PERRB to be

asserted.

P/N:PM0488

REV. 1.7, SEP. 15, 1998

3

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