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SC18IM700

Master I2C-bus controller with UART interface

NXP Semiconductors. 

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

9.2.2.4 Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port configured in this manner must have an external pull-up, typically a resistor

tied to VDD.

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

pin latch data

VSS

input data

Fig 16. Open-drain output configuration

GPIO pin

glitch rejection

002aab883

9.2.3 Programmable I/O pins state register (IOState)

When read, this register returns the actual state of all I/O pins. When written, each register

bit will be transferred to the corresponding I/O pin programmed as output.

Table 7.

Bit

7:0

IOState - Programmable I/O pins state register (address 0x04h) bit description

Symbol

Description

IOLevel

Set the logic level on the output pins.

Write to this register:

logic 0 = set output pin to zero

logic 1 = set output pin to one

Read this register returns states of all pins.

9.2.4 I2C-bus address register (I2CAdr)

The contents of the register represents the device’s own I2C-bus address. The most

significant bit corresponds to the first bit received from the I2C-bus after a START

condition. A logic 1 in I2CAdr corresponds to a HIGH level on the I2C-bus, and a logic 0

corresponds to a LOW level on the I2C-bus. The least significant bit is not used, but

should be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be configured so that its address

does not conflict with an I2C-bus device address used by the bus master.

9.2.5 I2C-bus clock rates (I2CClk)

This register determines the serial clock frequency. The various serial rates are shown in

Table 8. The frequency can be determined using the following formula:

bit frequency = ------------------7---.--3---7---2---8---------1---0----6------------------

(2)

2  I2CClkH + I2CClkL

I2CClkH determines the SCL HIGH period, and I2CClkL determines the SCL LOW period.

SC18IM700_3

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 — 12 October 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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