SC18IM700 Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
Lista de partido
SC18IM700 Datasheet PDF : 24 Pages
| |||
NXP Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
12. Dynamic characteristics
Table 13. I2C-bus timing characteristics
All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.4 V to 3.6 V;
Tamb = 40 C to +85 C; and refer to VIL and VIH with an input voltage of VSS to VDD.
Symbol Parameter
Conditions
Standard mode
I2C-bus
Fast mode Unit
I2C-bus
Min Max Min Max
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and START
condition
0
100
0
400 kHz
4.7
-
1.3
- s
tHD;STA
tSU;STA
tSU;STO
tHD;DAT
tVD;ACK
tVD;DAT
hold time (repeated) START condition
set-up time for a repeated START condition
set-up time for STOP condition
data hold time
data valid acknowledge time
data valid time
LOW-level
HIGH-level
4.0
-
0.6
- s
4.7
-
0.6
- s
4.0
-
0.6
- s
0
-
0
- ns
-
0.6
-
0.6 s
-
0.6
-
0.6 s
-
0.6
-
0.6 s
tSU;DAT
tLOW
tHIGH
tf
tr
tSP
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
250
-
100
- ns
4.7
-
1.3
- s
4.0
-
0.6
- s
-
0.3
-
0.3 s
-
1
-
0.3 s
-
50
-
50 ns
SDA
tf
SCL
S
tLOW
tr
tSU;DAT
tf
tHD;STA
tHD;STA
tHIGH tSU;STA
tHD;DAT
Sr
Fig 17. I2C-bus timing
tSP
tr
tBUF
tSU;STO
P
S
002aab271
SC18IM700_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 12 October 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
16 of 24
Share Link: 