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VG4632321A

524,288x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor 

VIS

Preliminary

VG4632321A

524,288x32x2-Bit

CMOS Synchronous Graphic RAM

DSF

D

Q

BankActivate CK

command

DQM0

DRAM

CELL

MR7

MR6

MR5

MR4

DQ7

DQ6

DQ5

DQ4

MR3

MR2

MR1

DQ3

DQ2

DQ1

MR0

DQ0

0 = Masked

1 = Not Masked

Note: Only lower byte is shown. The operation is identical for other bytes.

Write Per Bit (I/O Mask) Block Diagram

A write burst without auto precharge function may be interrupted by a subsequent Write/Block

Write, BankPrecharge/PrechargeAll, or Read command before the end of burst length. The interrupt

comes from Write/Block Write command can occur on any clock cycle following the previous Write

command ( refer to the following figure).

T0

T1

T2

T3

T4

T5

T6

T7

T8

CLK

COMMAND NOP

DQ’s

WRITE A WRITE B

1 Clk Interval

DIN A0

DIN B0

NOP

DIN B1

NOP

NOP

DIN B2

DIN B3

NOP

NOP

NOP

Write Interrupted by a Write (Burst Length = 4, CAS Latency = 1, 2, 3)

The Read command that interrupts a write burst without auto precharge function should

be issued one cycle after the clock edge at which the last data-in element is registered. In

order to avoid data contention, input data must be removed from the DQs at least one clock

cycle before the first read data appears on the outputs (refer to the following figure). Once the

Read command is registered, the data inputs will be ignored, and writes will not be executed.

Document:

Rev.1

Page 10

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