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VG4632321A

524,288x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor 

VIS

Preliminary

VG4632321A

524,288x32x2-Bit

CMOS Synchronous Graphic RAM

23,56,24,

57

DQM0-

DQM3

Input

Data Input/Output Mask: DQM0-DQM3 are byte specific, nonpersistent I/O buffer

controls. The I/O buffers are placed in a high-z state when DQM is sampled HIGH.

Input data is masked when DQM is sampled HIGH during a write cycle. Output data

is masked (two-clock latency) when DQM is sampled HIGH during a read cycle.

DQM3 masks DQ31-DQ24, DQM2 masks DQ23-DQ16, DQM1 masks DQ15-DQ8,

and DQM0 masks DQ7-DQ0.

97,98,100,

1,3,4,6,7,

60,61,63,

64,68,69,

71,72,9,

10,12,13,

17,18,20,

21,74,75,

77, 78,80,

81, 83, 84

DQ0-

DQ31

Input/ Data I/O: The DQ0-31 input and output data are synchronized with the positive

Output edges of CLK. The I/Os are byte-maskable during Reads and Writes. The DQs also

serve as column/byte mask inputs during Block Writes.

30,36-45, NC

52,58,

86-95

- No Connect: These pins should be left unconnected.

2,8,14,22,

59,67,73,

79

VDDQ

Supply DQ Power: Provide isolated power to DQs for improved noise immunity.

5,11,19,

62,70,76,

82,99

VSSQ

Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

15,35,65, VDD Supply Power Supply: +3.3V ±0.3V

96

16,46,66, VSS Supply Ground

85

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