VG4632321A Ver la hoja de datos (PDF) - Vanguard International Semiconductor
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VG4632321A Datasheet PDF : 81 Pages
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VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
NOP
NOP
DQ’s
: “H” or “L”
DOUT A0 Must be Hi-Z before
the Write Command
DINB0
DINB1
DINB2
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
1 Clk Interval
COMMAND
NOP
CAS Iatency = 1
tCK1,DQ’s
CAS Iatency = 2
tCK2,DQ’s
: “H” or “L”
NOP
BANK A
ACTIVATE
NOP
READ A
WRITE A
NOP
NOP
NOP
Must be Hi-Z before
the Write Command
DIN A0
DIN A0
DIN A1
DIN A2
DIN A3
DIN A1
DIN A2
DIN A3
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2)
CLK
DQM
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
NOP
NOP
READ A
NOP
NOP
WRITE B
NOP
NOP
NOP
CAS Iatency = 1
tCK1,DQ’s
CAS Iatency = 2
tCK2,DQ’s
: “H” or “L”
DOUT A0
Must be Hi-Z before
the Write Command
DIN B0
DIN B0
DIN B1
DINB2
DIN B3
DIN B1
DIN B2
DIN B3
Read to Write interval (Burst Length °Ÿ 4, CAS Latency = 1, 2)
A read burst without auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank. The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS latency.
Document:
Rev.1
Page 8
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