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VG4632321A Datasheet PDF : 81 Pages
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VIS
Preliminary
VG4632321A
524,288x32x2-Bit
CMOS Synchronous Graphic RAM
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
ADDRESS
Bank
Col A
COMMAND
READ A
NOP
NOP
Bank(s)
NOP
Precharge
t RP
NOP
NOP
Bank
Row
Activate
NOP
CAS Iatency = 1
tCK1,DQ’s
CAS Iatency = 2
tCK2,DQ’s
CAS Iatency = 3
tCK3,DQ’s
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1 DOUT A2
DOUT A3
Read to Precharge (CAS Latency = 1, 2, 3)
6 Read and AutoPrecharge command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A8 = ”H”, A0-A7 = Column Address, A9,A10 = Don’t
care)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command can not occur within a time delay of
{tRP(min.) + burst length}. At full-page burst, only read operation is performed in this command and the auto
precharge function is ignored.
7 Write command
(RAS = ”H”, CAS = ”L”, WE = ”L”, DSF = “L”, BS = Bank, A8 = ”L”, A0-A7 = Column Address, A9,A10 = Don’t
care)
The Write command is used to write burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remains high-impedance at the end of the burst, unless other command was initiated. The burst length and
burst sequence are determined by the mode register which is already programmed. A full-page burst will con-
tinue until terminated (at the end of the page it will wrap to column 0 and continue).
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DQ0 - DQ3
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
The first data element and the write
are registered on the same clock edge.
Extra data is masked.
Burst Write Operation (Burst Length = 4, CAS Latency = 1, 2, 3)
Any Write performed to a row that was opened via an BankAcitvate & Masked Write Enable command is a
masked write (Write-Per-Bit). Data is written to the 32 cells (bits) at the selected column location subject to the
data stored in the Mask register. The overall mask consists of the DQM inputs, which mask on a per-byte
basis, and the Mask register, which masks on a per-bit basis. This is shown in the following block diagram.
Document:
Rev.1
Page 9
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