RTL8208 Ver la hoja de datos (PDF) - Realtek Semiconductor
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RTL8208 Datasheet PDF : 40 Pages
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7.5.3 SS-SMII (Source Synchronous -Serial MII)
RTL8208
Source-Synchronous SMII is designed for applications requiring a trace delay of more than 1ns. Three signals are added to the
SMII interface: RX_SYNC, RX_CLK, TX_CLK; and the SYNC of SMII is modified to TX_SYNC in SS-SMII.
8-port
MAC
X1
TX_SYNC
TXD0[7:0]
TX_CLK
RX_SYNC
RXD0[7:0]
RX_CLK
REFCLK
RTL8208
125MHz
oscillator
SS-SMII Signal Diagram
Receive Path
Receive data and control information are signaled in 10-bit segments. RX_SYNC signal is used to delimit the 10-bit segments.
RTL8208 is responsible to generate these RX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a
byte of data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence
contains all of the information defined on the standard MII receive path.
1
2
3
4
5
6
7
8
9
10
RX_CLK
RX_SYNC
RXD[0]
CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
SS-SMII Reception
Transmit Path
Transmit data and control information are signaled in 10-bit segments. TX_SYNC signal is used to delimit the 10-bit segments.
MAC is responsible to generate these TX_SYNC pulses every ten clocks. For 100Mbps mode, each segment represents a byte of
data. However, for 10Mbps mode, each segment is repeated ten times to represent a byte of data. The receive sequence contains
all of the information defined on the standard MII receive path. The PHY can sample one of the ten segments.
1
2
3
4
5
6
7
8
9
10
TX_CLK
TX_SYNC
TXD[0] TX_ER TX_EN TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7
SS-SMII Transmission
Collision Detection
The RTL8208 does not indicate that a collision has occurred. It is left up to the MAC to detect the assertion of both CRS_DV and
TX_EN.
2003/04/04
27
Rev.1.97
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