RTL8208 Ver la hoja de datos (PDF) - Realtek Semiconductor
Número de pieza
componentes Descripción
Lista de partido
RTL8208 Datasheet PDF : 40 Pages
| |||
RTL8208
7.6.1 RMII (Reduced MII)
The RTL8208 meets all of the RMII requirements outlined in the RMII Consortium specifications. The main advantage
introduced by RMII is pin count reduction; e.g., it operates with only one 50Mhz reference clock for both the TX and RX sides
without separate clocks needed for both paths, as with the MII interface. However, some hardware modification is needed for
this change, the most important and outstanding of which is the presence of an elastic buffer for absorption of the frequency
difference between the 50MHz reference clock and the clocking information of the incoming data stream. Another change
implemented is that the MII RXDV and Carrier_Sense are merged into one signal, CRS_DV, which is asserted high while
detecting incoming packet data. When internal Carrier_Sense de-asserted, CRS_DV is de-asserted when the first di-bit of a
nibble is presented onto RXD[1:0] synchronously to REFCLK. If there is still data in the FIFO that has not yet been presented
onto RXD[1:0], then on the second di-bit of a nibble CRS_DV reasserts. This pattern of assertion and de-assertion continues
until all received data in the FIFO has been presented onto RXD[1:0]
RTL8208
X1
CRS_DV[7:0]
RXD0[7:0]
RXD1[7:0]
TX_EN[7:0]
TXD0[7:0]
TXD1[7:0]
REFCLK
8-port
MAC
RTL8208
X1
X2
25MHz
CRS_DV[7:0]
RXD0[7:0]
RXD1[7:0]
TX_EN[7:0]
TXD0[7:0]
TXD1[7:0]
REFCLK
8-port
MAC
50MHz
oscillator
RMII Signal Diagram
50MHz Oscillator Solution
RMII Signal Diagram
25MHz Crystal Solution
7.6.2 SMII (Serial MII)
The RTL8208 also supports SMII interface to MAC, which allows a further reduction in the number of signals. As illustrated
below, both the MAC and RTL8208 are synchronous to a 125MHz reference clock.
SYNC
TXD0[7:0]
8-port
MAC
X1
RXD0[7:0]
RTL8208
REFCLK
125MHz
oscillator
SMII Signal Diagram
2003/04/04
25
Rev.1.97
Share Link: 