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RTL8208

REALTEK SINGLE CHIP OCTAL 10/100 MBPS FAST ETHERNET TRANSCEIVER

Realtek Semiconductor 

RTL8208

7.5.3 Link Monitor

In 100Base-FX mode, if the RTL8208 receive path detects a valid link word, it enters the link state. If no valid link word is

detected, it is in a link down state. Therefore, SD+/- is not necessary. The RTL8208 uses a reduced 100Base-FX interface.

7.5.4 Far-End-Fault-Indication (FEFI)

The MII Register 1.4 (Remote Fault indication detected) is a FEFI bit when 100FX is enabled, which indicates FEFI has been

detected. FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the

point of view of the RTL8208, once this pattern is detected 3 times, Register 1.4 is set, which means the transmit path (Remote

side’s receive path) has some problems.

On the other hand, if the RTL8208 detects no valid link pulse on RxOP/N pair, it sends out a FEFI stream pattern, which in turn

will cause the remote side to detect a Far-End-Fault indication. This means the RTL8208 sees problems on the receive path.

The FEFI mechanism is used only in 100Base-FX applications.

7.5.5 Reduced Fiber Interface

The.RTL8208 ignores the underlying SD signal of the fiber transceiver to complete link detection and connection. This is

achieved by monitoring RD signals from the fiber transceiver and checking if any link integrity events are met. This significantly

reduces pin-count, especially for high-port PHY devices. This is a Realtek patent-pending technology and available only with

Realtek product solutions.

7.6 RMII/SMII/SS-SMII

The interface to the MAC can be RMII, SMII, or SS-SMII through MODE[1:0]. When floating MODE[1:0] upon power-on reset,

the RTL8208 operates in RMII mode (default).

MODE[1:0]

2’b1x

2’b00

2’b01

Operation Mode

RMII

SMII

SS-SMII

REFCLK Clock input

50MHz, 100ppm

125MHz, 100ppm

125MHz, 100ppm

Below illustrates the signals required for each interface:

RMII

REFCLK

CRS_DV[3:0]

CRS_DV[4]

CRS_DV[7:5]

RXD0[7:0]

RXD1[7:0]

TX_EN[3:0]

TX_EN[4]

TX_EN[7:5]

TXD0[7:0]

TXD1[7:0]

SMII

REFCLK

SYNC

RXD0[7:0]

TXD0[7:0]

SS-SMII

REFCLK

TX_SYNC

RX_SYNC

RX_CLK

RXD0[7:0]

TX_CLK

TXD0[7:0]

2003/04/04

24

Rev.1.97

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