A43L8316V Ver la hoja de datos (PDF) - AMIC Technology

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A43L8316V

128K X 16 Bit X 2 Banks Synchronous DRAM

AMIC Technology 

Read & Write Cycle at Same Bank @Burst Length=4

A43L8316

0

CLOCK

CKE

CS

RAS

CAS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

*Note 1

tRC

High

tRCD

*Note 2

ADDR

Ra

Ca0

Rb

Cb0

BA

A8/AP

Ra

Rb

WE

DQM

DQ

(CL = 2)

DQ

(CL = 3)

tRAC

*Note 3 tSAC

tOH

Qa0

Qa1

Qa2

Qa3

tSHZ

*Note 4

tRAC

*Note 3

tSAC

tOH

Qa0

Qa1

Qa2

Qa3

tSHZ

*Note 4

Db0

Db1

Db2 Db3

tRDL

Db0

Db1

Db2 Db3

tRDL

Row Active

(A-Bank)

Read

(A-Bank)

Precharge

(A-Bank)

Row Active

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS latency-1] valid output data available after Row

enters precharge. Last valid output will be Hi-Z after tSHZ from the clock.

3. Access time from Row address. tCC*(tRCD + CAS latency-1) + tSAC

4. Output will be Hi-Z after the end of burst. (1,2,4 & 8)

At Full page bit burst, burst is wrap-around.

Preliminary (April, 2000, Version 1.0)

25

AMIC Technology, Inc.

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