Page Write Cycle at Different Bank @Burst Length=4
A43L8316
0
CLOCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CKE
High
CS
RAS
CAS
ADDR
RAa
BA
A8/AP
RAa
DQ
WE
DQM
CAa RBb
CBb
CAc
CBd
*Note 2
RBb
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
tCDL
tRDL
*Note 1
Row Active with
(A-Bank)
Row Active
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Write
(A-Bank)
Precharge
(Both Banks)
Write
(B-Bank)
: Don't care
* Note:
1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and precharge banks must be the same.
Preliminary (April, 2000, Version 1.0)
28
AMIC Technology, Inc.