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AM79C961KCW

PCnet™-ISA+ Jumperless Single-Chip Ethernet Controller for ISA

Advanced Micro Devices 

AMD

PRELIMINARY

BOARD INTERFACE

APCS/IRQ15

Address PROM Chip Select

Output

This signal is asserted when the external Address

PROM is read. When an I/O read operation is per-

formed on the first 16 bytes in the PCnet-ISA+

controller’s I/O space, APCS is asserted. The outputs of

the external Address PROM drive the PROM Data Bus.

The PCnet-ISA+ controller buffers the contents of the

PROM data bus and drives them on the lower eight bits

of the System Data Bus. IOCS16 is not asserted during

this cycle.

BPAM

Boot PROM Address Match

Input

This pin indicates a Boot PROM access cycle. If no Boot

PROM is installed, this pin has a default value of HIGH

and thus may be left connected to VDD.

BPCS

Boot PROM Chip Select

Output

This signal is asserted when the Boot PROM is read. If

BPAM is active and MEMR is active, the BPCS signal

will be asserted. The outputs of the external Boot

PROM drive the PROM Data Bus. The PCnet-ISA+ con-

troller buffers the contents of the PROM data bus and

drives them on the System Data Bus. IOCS16 is not as-

serted during this cycle. If 16-bit cycles are performed, it

is the responsibility of external logic to assert MEMCS16

signal.

DXCVR/EAR

Disable Transceiver/

External Address Reject

Input/Output

This pin disables the transceiver. The DXCVR output is

configured in the initialization sequence. A high level in-

dicates the Twisted Pair Interface is active and the AUI

is inactive, or SLEEP mode has been entered. A low

level indicates the AUI is active and the Twisted Pair in-

terface is inactive.

If EADI mode is selected, this pin becomes the EAR

input.

The incoming frame will be checked against the inter-

nally active address detection mechanisms and the

result of this check will be OR’d with the value on the

EAR pin. The EAR pin is defined as REJECT. (See the

EADI section for details regarding the function and tim-

ing of this signal.)

LED0-3

LED Drivers

Output

These pins sink 12 mA each for driving LEDs. Their

meaning is software configurable (see section The ISA

Bus Configuration Registers) and they are active LOW.

When EADI mode is selected, the pins named LED1,

LED2, and LED3 change in function while LED0 contin-

ues to indicate 10BASE-T Link Status. The DXCVR

input becomes the EAR input.

LED

EADI Function

1

SF/BD

2

SRD

3

SRDCLK

PRAB0-15

Private Address Bus

Input/Output

The Private Address Bus is the address bus used to

drive the Address PROM, Remote Boot PROM, and

SRAM. PRAB10-15 are required to be buffered by a Bus

Buffer with ABOE as its control and SA10-15 as its

inputs.

PRDB3-7

Private Data Bus

Input/Output

This is the data bus for the static RAM, the Boot PROM,

and the Address PROM.

PRDB2/EEDO

Private Data Bus Bit 2/Data Out Input/Output

A multifunction pin which serves as PRDB2 of the pri-

vate data bus and, when ISACSR3 bit 4 is set, changes

to become DATA OUT from the EEPROM.

PRDB1/EEDI

Private Data Bus Bit 1/Data In Input/Output

A multifunction pin which serves as PRDB1 of the pri-

vate data bus and, when ISACSR3 bit 4 is set, changes

to become DATA In to the EEPROM.

PRDB0/EESK

Private Data Bus Bit 0/

Serial Clock

Input/Output

A multifunction pin which serves as PRDB0 of the pri-

vate data bus and, when ISACSR3 bit 4 is set, changes

to become Serial Clock to the EEPROM.

SHFBUSY

Shift Busy

Input/Output

An output from PCnet-ISA+ which indicates that a read

from the external EEPROM is in progress. It is active

only when the hardware reconfigure is running (when

data is being shifted out of the EEPROM due to a hard-

ware RESET or the EELOAD command being issued).

SHFBUSY should be connected to VCC with a 10K Ω

resistor.

EECS

EEPROM CHIPSELECT

Output

This signal is asserted when read or write accesses are

being performed to the EEPROM. It is controlled by

ISACSR3. It is driven at Reset during EEPROM Read.

SLEEP

Sleep

Input

When SLEEP input is asserted (active LOW), the

PCnet-ISA+ controller performs an internal system reset

1-500

Am79C961

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