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AM79C961KCW Datasheet PDF : 173 Pages
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PRELIMINARY
AMD
FUNCTIONAL DESCRIPTION
The PCnet-ISA+ controller is a highly integrated system
solution for the PC-AT ISA architecture. It provides an
Ethernet controller, AUI port, and 10BASE-T trans-
ceiver. The PCnet-ISA+ controller can be directly
interfaced to an ISA system bus. The PCnet-ISA+ con-
troller contains an ISA bus interface unit, DMA Buffer
Management Unit, 802.3 Media Access Control func-
tion, separate 136-byte transmit and 128-byte receive
FIFOs, IEEE defined Attachment Unit Interface (AUI),
and Twisted-Pair Transceiver Media Attachment Unit.
In addition, a Sleep function has been incorporated
which provides low standby current for power sensitive
applications.
The PCnet-ISA+ controller is register compatible with
the LANCE (Am7990) Ethernet controller and
PCnet-ISA (Am79C960). The DMA Buffer Manage-
ment Unit supports the LANCE descriptor software
model and the PCnet-ISA+ controller is software com-
patible with the Novell NE2100 and NE1500T add-in
cards.
External remote boot PROMs and Ethernet physical ad-
dress PROMs are supported. The location of the I/O
registers, Ethernet address PROM, and the boot PROM
are determined by the programming of the registers in-
ternal to PCnet-ISA+. These registers are loaded at
RESET from the EEPROM.
Normally, the Ethernet physical address will be stored in
the EEPROM with the other configuration data. This re-
duces the parts count, board space requirements, and
power consumption. The option to use a standard paral-
lel 8 bit PROM is provided to manufactures who are
concerned about the non-volatile nature of EEPROMs.
The PCnet-ISA+ controller’s bus master architecture
brings to system manufacturers (adapter card and
motherboard makers alike) something they have not
been able to enjoy with other architectures—a low-cost
system solution that provides the lowest parts count and
highest performance. As a bus-mastering device, costly
and power-hungry external SRAMs are not needed for
packet buffering. This results in lower system cost due
to fewer components, less real-estate and less power.
The PCnet-ISA+ controller’s advanced bus mastering
architecture also provides high data throughput and low
CPU utilization for even better performance.
To offer greater flexibility, the PCnet-ISA+ controller has
a shared memory mode to meet varying application
needs. The shared memory architecture is compatible
with very low-end machines, such as PC/XTs that do not
support bus mastering, and very high end machines
which require local packet buffering for increased sys-
tem latency.
The network interface provides an Attachment Unit In-
terface and Twisted-Pair Transceiver functions. Only
one interface is active at any particular time. The AUI
allows for connection via isolation transformer to
10BASE5 and 10BASE2, thick and thin based coaxial
cables. The Twisted-Pair Transceiver interface allows
for connection of unshielded twisted-pair cables as
specified by the Section 14 supplement to IEEE 802.3
Standard (Type 10BASE-T).
Bus Master Mode
System Interface
The PCnet-ISA+ controller has two fundamental operat-
ing modes, Bus Master and Shared Memory. The
selection of either the Bus Master mode or the Shared
Memory mode must be done through hard wiring; it is
not software configurable. The Bus Master mode pro-
vides an Am7990 (LANCE) compatible Ethernet
controller, an Ethernet Address EEPROM or PROM, a
Boot PROM, and a set of device configuration registers.
The optional Boot PROM is in memory address space
and is expected to be 8–64K. On-chip address com-
parators control device selection based on the value of
the EEPROM.
The address PROM, board configuration registers, and
the Ethernet controller occupy 24 bytes of I/O space and
can be located on 16 different starting addresses.
Data buffers are located in system memory and can be
accessed by the PCnet-ISA+ controller when the device
becomes the Current Master.
Am79C961
1-503

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